A circuit may include a memory cell. The memory cell may include a first memory element, a second memory element, a first transistor, and a second transistor. The first memory element may be connected to a bit line. The second memory element may be connected to a select line. The first transistor may be connected to a first word line. The second transistor may be connected to a second word line. The first memory element may be programmed by applying a first write voltage to the bit line, applying a second write voltage to the second word line, applying a first intermediate voltage to the select line, and applying a second intermediate voltage to the first word line. The select line may be connected to a high impedance. The first write voltage may be a positive supply voltage, the second write voltage may be a negative supply voltage.

Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.

Structures including non-volatile memory elements and methods of fabricating a structure including non-volatile memory elements. First, second, and third non-volatile memory elements each include a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. A first bit line is coupled to the first electrode of the first non-volatile memory element and to the first electrode of the second non-volatile memory element. A second bit line is coupled to the first electrode of the third non-volatile memory element.

A memory device includes a plurality of circuit layers, a plurality of first conductive through via structures and a plurality of bitlines. The circuit layers are disposed one above another, and each circuit layer includes one or more memory cell arrays. The first conductive through via structures penetrates though the circuit layers. Each of the bitlines includes a plurality of bitline segments disposed on the circuit layers respectively. The bitline segments are electrically connected through one of the first conductive through via structures. Each bitline segment is coupled to a plurality of memory cells of a memory cell array of a circuit layer where the bitline segment is disposed.

Disclosed herein are devices, systems, and methods that provide improved tunneling magnetoresistance (TMR) through the use of innovative device structures and heterostructure layers therein. Particularly, two or more magnetic layers form a heterostructure core of the switching device, with control of current passing through the heterostructure determined by an applied magnetic field that modifies the magnetization of the heterostructure from a ground magnetic state that is layered antiferromagnetic.

Disclosed are a synthetic antiferromagnetic material using the Ruderman-Kittel-Kasuya-Yosida (RKKY) interaction and a multibit memory using the synthetic antiferromagnetic material that is formed. The synthetic antiferromagnetic material has a non-magnetic metal layer as an RKKY inducing layer in the center, interaction between upper and lower ferromagnetic layers is imparted according to the thickness of the RKKY inducing layer, and the magnetization of an anti-parallel state is maximized therebetween. When such synthetic antiferromagnetic materials are cumulatively stacked and tunnel barrier layers are provided therebetween, multiple bits can be stored. Namely, data may be stored by supplying a program current in parallel to the surface of the RKKY inducing layer, and a resistance state may be checked by supplying current in a vertical direction to the surface of the RKKY inducing layer.

The present disclosure provides a multi-bit memory cell, an analog-to-digital converter, a device and a method. The multi-bit memory cell comprises: a spin-orbit coupling layer and a plurality of magnetic tunnel junctions disposed on the spin-orbit coupling layer, the plurality of magnetic tunnel junctions comprising a plurality of first magnetic tunnel junctions; the plurality of first magnetic tunnel junctions are sequentially arranged along a length direction of the spin-orbit coupling layer, and critical currents of reversals of the magnetizations of free layers of the plurality of first magnetic tunnel junctions are progressively increased or decreased in sequence along the length direction. The present disclosure provides a multi-bit memory unit with simple manufacturing process and structure.

Methods, systems, and devices for programming techniques for polarity-based memory cells are described. A memory device may use a first type of write operation to program one or more memory cells to a first state and a second type of write operation to program one or more memory cells to a second state. Additionally or alternatively, a memory device may first attempt to use the first type of write operation to program one or more memory cells, and then may use the second type of write operation if the first attempt is unsuccessful.

A MTJ device includes a free (storage) magnet and fixed (reference) magnet between first and second electrodes, and a programmable booster between the free magnet and one of the electrodes. The booster has a magnetic material layer. The booster may further have an interface layer that supports the formation of a skyrmion spin texture, or a stable ferromagnetic domain, within the magnetic material layer. A programming current between two circuit nodes may be employed to set a position of the skyrmion or magnetic domain within the magnetic material layer to be more proximal to, or more distal from, the free magnet. The position of the skyrmion or magnetic domain to the MTJ may modulate TMR ratio of the MTJ device. The TMR ratio modulation may be employed to discern more than two states of the MTJ device. Such a multi-level device may, for example, be employed to store 2 bits/cell.

Magnetic random access memory (MRAM) cells are provided. MRAM cell includes a plurality of stacked magnetic tunnel junction (MTJ) devices coupled in serial, and a transistor. The transistor has a gate coupled to a word line, a first terminal coupled to a bit line through the stacked MTJ devices, and a second terminal coupled to a source line. The stacked MTJ devices have different sizes. Each of the stacked MTJ devices includes a free layer, a pinned layer and a barrier layer between the free layer and the pinned layer. The free layers of two adjacent stacked MTJ devices are in direct contact with each other.