According to one embodiment, a variable resistance element includes first and conductive layers and first and second layers. The first conductive layer includes a first element including at least one selected from the group consisting of silver, copper, aluminum, nickel, and titanium. The second conductive layer includes at least one selected from the group consisting of platinum, gold, iridium, tungsten, palladium, rhodium, titanium nitride, and silicon. A first layer contacts the first conductive layer, and is provided between the first and second conductive layers. The first layer includes a first material. The first material is insulative. The second layer includes a second element and a second material and is provided between the first layer and the second conductive layer. The second element includes at least one selected from the group consisting of silver, copper, aluminum, nickel, and titanium. The second material is different from the first material.

Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.

Devices and methods for accessing resistive change elements in a resistive change element array to determine resistive states of the resistive change elements are disclosed. According to some aspects of the present disclosure the devices and methods access resistive change elements in a resistive change element array through a variety of operations. According to some aspects of the present disclosure the devices and methods supply an amount of current tailored for a particular operation. According to some aspects of the present disclosure the devices and methods compensate for circuit conditions of a resistive change element array by adjusting an amount of current tailored for a particular operation to compensate for circuit conditions of the resistive change element array.

In one embodiment, a cached memory device can include: (i) a memory array coupled to a system address bus and an internal data bus; (ii) a plurality of data buffers coupled to a system data bus, and to the memory array via the internal data bus; (iii) a plurality of valid bits, where each valid bit corresponds to one of the data buffers; (iv) a plurality of buffer address registers coupled to the system address bus, where each buffer address register corresponds to one of the data buffers; and (v) a plurality of compare circuits coupled to the system address bus, where each compare circuit corresponds to one of the data buffers.

Devices and methods for accessing resistive change elements in a resistive change element array to determine resistive states of the resistive change elements are disclosed. According to some aspects of the present disclosure the devices and methods access resistive change elements in a resistive change element array through a variety of operations. According to some aspects of the present disclosure the devices and methods supply an amount of current tailored for a particular operation. According to some aspects of the present disclosure the devices and methods compensate for circuit conditions of a resistive change element array by adjusting an amount of current tailored for a particular operation to compensate for circuit conditions of the resistive change element array.

According to one embodiment, a resistance change memory device comprises a memory cell array in which a plurality of resistance change storage elements each to store one of multiple resistance states as data represented in two or more bits are arranged, and a read unit to read the data of a selected one of the storage elements. In reading the data of the storage element, the read unit, selecting one at a time, applies multiple types of constant voltages to the storage element.

A memory device includes: a first conductive layer extending in a first direction, and a second conductive layer extending in a second direction intersecting with the first direction. A third conductive layer is electrically connected to the second conductive layer. A variable resistance layer includes a first layer containing a semiconductor or a first metal oxide and a second layer located between the first layer and the second conductive layer and containing a second metal oxide. The second layer includes a first end and a second end spaced from the third conductive layer farther than the first end. An intermediate layer is provided between the variable resistance layer and the second conductive layer and has a resistivity higher than that of the second layer. An insulator is provided between the first end and the second conductive layer and has a resistivity higher than that of the second layer.

Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.

A vertical interconnect via having a first array of first metal interconnect wires extending along a first lateral direction made from a first material and a second array of second interconnect wires extending along a second lateral direction made from a second material. An intersection defined by the first array and the second array, wherein each intersection of the first array and the second array defines a metal-insulator-metal structure. The said metal-insulator-metal structure transforms to metal-metal-metal structure upon an application of electric pulse.

A detection circuit that can detect a two-terminal memory cell changing state. For example, in response to electrical stimuli, a memory cell will change state, e.g., to a defined higher resistance state or a defined lower resistance state. Other, techniques do not detect this state change until after the stimuli is completed and a subsequent sensing operation (e.g., read pulse) is performed. The detection circuit can detect the state change during application of the electrical stimuli that cause the state change and can do so by comparing the magnitudes or values of two particular current parameters.