An enhanced ferroelectric transistor may include Interface switching modulation (ISM) layers along with a ferroelectric layer in the gate of the transistor to increase a memory window while maintaining relatively low operating voltages. The enhanced ferroelectric transistor may be implemented as a memory device storing more than two bits of information in each memory cell. An enhanced ferroelectric tunnel junction device may include ISM layers and a ferroelectric layer to amplify the tunneling barriers in the device. The ISM layers may form material dipoles that add to the effect of ferroelectric dipoles in the ferroelectric material.

Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.

A vertical semiconductor device includes: a channel on a substrate, the channel extending in a first direction substantially perpendicular to an upper surface of the substrate; a first data storage structure contacting a first sidewall of the channel; a second data storage structure on a second sidewall of the channel; and gate patterns on a surface of the second data storage structure, wherein the gate patterns are spaced apart from each other in the first direction, and the gate patterns extend in a second direction substantially parallel to the upper surface of the substrate.

Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.

A resistive random-access memory (ReRAM) device may include a thermally engineered layer that is positioned adjacent to an active layer and configured to act as a heat sink during filament formation in response to applied voltages. The thermally engineered layer may act as one of the electrodes on the ReRAM device and may be adjacent to any side of the active layer. The active layer may also include a plurality of individual active layers. Each of the active layers may be associated with a different dielectric constant, such that the middle active layer has a dielectric constant that is significantly higher than the other two surrounding active layers.

Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.

A vertical nonvolatile memory device including memory cell strings using a resistance change material is provided. Each of the memory cell strings of the nonvolatile memory device includes a semiconductor layer extending in a first direction; a plurality of gates and a plurality of insulators alternately arranged in the first direction; a gate insulating layer extending in the first direction between the plurality of gates and the semiconductor layer and between the plurality of insulators and the semiconductor layer; and a resistance change layer extending in the first direction on a surface of the semiconductor layer. The resistance change layer includes a metal-semiconductor oxide including a mixture of a semiconductor material of the semiconductor layer and a transition metal oxide.

A programmable resistive memory element and a method of adjusting a resistance of a programmable resistive memory element are provided. The programmable resistive memory element includes at least one resistive memory element. Each resistive memory element includes an Indium-Gallium-Zinc-Oxide (IGZO) resistive layer, a first electrical contact and a second electrical contact. The first and second electrical contacts are disposed on the IGZO resistive layer in the same plane. The programmable resistive memory element includes a voltage generator coupled to the first and second electrical contacts, constructed and arranged to apply a thermal treatment to the resistive memory element to adjust a resistance of the resistive memory element.

A resistive random access memory is provided. The resistive random access memory includes a substrate, a first electrode formed on the substrate, a second electrode formed on the substrate and located on one side of the first electrode, a first metal oxide layer formed on sidewalls of the second electrode, a first control layer formed between the first electrode and the first metal oxide layer, and a second control layer formed on the first control layer and located between the first electrode and the first metal oxide layer.

The present invention discloses a multi-bit-per-cell three-dimensional resistive random-access memory (3D-RRAM.sub.MB). It comprises a plurality of RRAM cells stacked above a semiconductor substrate. Each RRAM cell comprises a RRAM layer, which is switched from a high-resistance state to a low-resistance state during programming. By adjusting the programming current, the programmed RRAMs have different resistances.