The present invention discloses a memristor array, comprising metal wires and memristors; the metal wires are arranged laterally and vertically; a memristor is arranged at the intersection of every two metal wires; the connection/disconnection of the metal wires is judged according to the resistance values of the memristors; and an adder is constituted according to the resistance value states of the memristors. The present invention provides a memristor-CMOS hybrid multiplication core circuit, in which one input of multiplication can be stored in a memristor network, one part of operation is completed in a memory network, the other part of operation is completed through a CMOS circuit, thereby reducing frequent data calls by half, and the power consumption of the CMOS circuit is further reduced by reducing competitive adventure in the operation process, thereby greatly reducing the overall energy consumption.

Systems, devices, circuits, methods, and non-transitory computer readable media that enable storing and searching arbitrary segments of ranges of analog values are disclosed. Various analog content addressable memory (aCAM) circuit implementations having the capability to store and search outside of a range of values, within any of multiple disjoint ranges, or outside of multiple ranges are disclosed. The disclosed aCAM circuit implementations make searching for complex input features more flexible and efficient, thereby yielding a technological improvement over conventional solutions. In some implementations, an aCAM may include multiple pull-down transistors connected in series to a match line that is pre-charged, in which case, the aCAM detects a match if the match line is not discharged by the pull-down transistors, which occurs if at least one pull-down transistor is in an OFF state. In other implementations, an aCAM includes pass gates connected to a match line to detect a match.

A memory circuit configured to perform multiply-accumulate (MAC) operations for performance of an artificial neural network includes a series of synapse cells arranged in a cross-bar array. Each cell includes a memory transistor connected in series with a memristor. The memory circuit also includes input lines connected to the source terminal of the memory transistor in each cell, output lines connected to an output terminal of the memristor in each cell, and programming lines coupled to a gate terminal of the memory transistor in each cell. The memristor of each cell is configured to store a conductance value representative of a synaptic weight of a synapse connected to a neuron in the artificial neural network, and the memory transistor of each cell is configured to store a threshold voltage representative of a synaptic importance value of the synapse connected to the neuron in the artificial neural network.

An array device and a writing method thereof are provided. A synapse array device includes: a crossbar array, in which a resistive memory element is connected to each intersection of a plurality of row lines and a plurality of column lines; a row select/drive circuit selecting a row line of the crossbar array and applying a pulse signal to the selected row line; a column select/drive circuit selecting a column line of the crossbar array and applying a pulse signal to the selected column line; and a writing part writing to the resistive memory element connected to the selected row line and the selected column line. A first write voltage with controlled pulse width is applied to the selected row line, and a second write voltage with controlled pulse width is applied to the selected column line to perform set writing of the resistive memory element.

A memory device includes a memory cell and a first select transistor. The memory cell includes a variable resistance memory region, a first semiconductor layer being in contact with the variable resistance memory region, a first insulating layer being in contact with the first semiconductor layer, and a first voltage application electrode being in contact with the first insulating layer. The first select transistor includes a second semiconductor layer, a second insulating layer being in contact with the second semiconductor layer, and a second voltage application electrode extending in the second direction and being in contact with the second insulating layer.

Various embodiments of the present disclosure are directed towards a method for forming a memory device. The method includes forming a bottom electrode over a substrate. A data storage structure is formed on the bottom electrode. The data storage structure comprises a first atomic percentage of a first dopant and a second atomic percentage of a second dopant. The first atomic percentage is different from the second atomic percentage. A top electrode is formed on the data storage structure.

Disclosed herein are a Gaussian sampling apparatus and method based on resistive RAM. The Gaussian sampling apparatus based on resistive RAM includes Resistive RAM (RRAM) in which a resistive switching layer is disposed between an upper electrode and a lower electrode, and a sampling controller, wherein the sampling controller is configured to perform an operation corresponding to an erase command of applying a reset voltage to the RRAM when a Gaussian error request is received from an outside of the Gaussian sampling apparatus, perform an operation corresponding to a program command of applying a set voltage to the RRAM after the operation corresponding to the erase command has been completed, perform an operation of reading resistance data from the RRAM, and provide a response to the outside of the Gaussian sampling apparatus by transmitting the resistance data of the RRAM as Gaussian error data.

Various embodiments of the present disclosure are directed towards a memory device including a first memory element and a second memory element. The memory device includes a substrate and a bottom electrode disposed over the substrate. The first memory element is disposed between the bottom electrode and a top electrode, such that the first memory element has a first area. A second memory element is disposed between the bottom electrode and the top electrode. The second memory element is laterally separated from the first memory element by a non-zero distance. The second memory element has a second area different than the first area.

Apparatuses and methods can be related to implementing a binary neural network in memory. A binary neural network can be implemented utilizing a resistive memory array. The memory array can comprise programmable memory cells that can be programed and used to store weights of the binary neural network and perform operations consistent with the binary neural network. The weights of the binary neural network can correspond to non-zero values.

Disclosed are a neuromorphic device and a unit synapse devices forming the same. The unit synapse device has a learning device and an inference device. The learning device and the inference device may share a via oxide layer and a common electrode, and a learning operation and an inference operation may be performed in one unit synapse device.