A resistive switching memory device according to an exemplary embodiment includes: a first electrode; a second electrode formed to be separated from the first electrode; and an insulating layer formed near the first electrode and the second electrode, and changed to one of a high resistance state and a low resistance state when a conductive filament is controlled by a change of external humidity or a voltage applied through the first electrode or the second electrode.

An electrically actuated switch comprises a first electrode, a second electrode, and an active region disposed therebetween. The active region comprises at least one primary active region comprising at least one material that can be doped or undoped to change its electrical conductivity, and a secondary active region comprising at least one material for providing a source/sink of ionic species that act as dopants for the primary active region(s). Methods of operating the switch are also provided.

Examples may include techniques to implement a SET write operation to a selected memory cell include in a memory array. Examples include selecting the memory cell that includes phase change material and applying various currents over various periods of time during a nucleation stage and a crystal growth stage to cause the memory cell to be in a SET logical state.

There are provided a variable resistance memory device and a manufacturing method of the same. The variable resistance memory device includes: a first electrode; a second electrode arranged in a vertical direction from the first electrode; and an oxide layer having an oxygen deficient region extending in the vertical direction between the second electrode and the first electrode.

Apparatuses and methods can be related to implementing a Bayesian neural network in a memory. A Bayesian neural network can be implemented utilizing a resistive memory array. The memory array can comprise programmable memory cells that can be programed and used to store weights of the Bayesian neural network and perform operations consistent with the Bayesian neural network.

An atomic orbital based memory storage is provided that includes a plurality of surface atoms forming dangling bonds (DBs) and a subset of the plurality of surface atoms passivated with spatial control to form covalent bonds with hydrogen, deuterium, or a combination thereof. The atomic orbital based data storage that can be rewritten and corrected as needed. The resulting data storage is also archival and capable of high data densities than any known storage as the data is retained in a binary storage or a given orbital being passivated or a dangling bond (DB). A method of forming and reading the atomic orbital data storage is also provided. The method including selectively removing covalent bonds to form dangling bonds (DBs) extending from a surface atom by hydrogen lithography and imaging the covalent bonds spatially to read the atomic orbital data storage.

A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.

A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.

Some embodiments include a memory cell having a non-ohmic device between a transistor source/drain region and a capacitor. Some embodiments include a memory cell having a transistor with a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. A capacitor is electrically coupled to the second source/drain region through a non-ohmic device. The non-ohmic device includes a non-ohmic-device-material which changes conductivity in response to an electrical property along the channel region. The non-ohmic-device-material has a high-resistivity-mode when the electrical property along the channel region is below a threshold level, and transitions to a low-resistivity-mode when the electrical property along the channel region meets or exceeds the threshold level. Some embodiments include a memory array.

Some embodiments include a memory cell having a non-ohmic device between a transistor source/drain region and a capacitor. Some embodiments include a memory cell having a transistor with a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. A capacitor is electrically coupled to the second source/drain region through a non-ohmic device. The non-ohmic device includes a non-ohmic-device-material which changes conductivity in response to an electrical property along the channel region. The non-ohmic-device-material has a high-resistivity-mode when the electrical property along the channel region is below a threshold level, and transitions to a low-resistivity-mode when the electrical property along the channel region meets or exceeds the threshold level. Some embodiments include a memory array.