Exemplary apparatus includes a nonvolatile memory, a volatile memory separate from the nonvolatile memory, and a controller configured to access the volatile memory and the nonvolatile memory. Exemplary volatile memory is configured to function as a read/write cache. The controller may be configured to perform a read/modify/write memory operation that involves both the volatile memory and the nonvolatile memory. Exemplary devices may have a host interface and may include a data connection configured to perform double data rate data transfer. Exemplary volatile memory may support byte-granularity memory read operations, and the density of the volatile memory may be substantially less than the density of the nonvolatile memory.

A semiconductor memory includes a substrate including a cell region, a first peripheral circuit region, and a second peripheral circuit region; a plurality of first lines disposed over the substrate across the cell region and the first peripheral circuit region; a plurality of second lines disposed over the first lines across the cell region and the second peripheral circuit region; and a first memory cell positioned at each of intersections between the first lines and the second lines, wherein the cell region includes a first cell region and a second cell region, the first cell region being disposed closer to the first and second peripheral circuit regions than the second cell region, and wherein a first portion of the second line that is in the first cell region has a greater resistance than a second portion of the second line that is in the second cell region.

Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is split into left and right portions. Each portion is electrically connected to a single via, which a driver uses to generate a voltage on the access line. To reduce electrical discharge associated with current spikes, a first resistor is located between the left portion and the via, and a second resistor is located between the right portion and the via.

In accordance with the present disclosure, one embodiment includes a memristor that is caused to be in a particular resistance state by a voltage applied across terminals of the memristor. A first logical input and a second logical input that are below a threshold voltage of the memristor are applied to a first terminal of the memristor. A first control input and a second control input are applied to a second terminal of the memristor. A logical output is determined based on a resistance state of the memristor.

A memory unit with an asymmetric group-modulated input scheme and a current-to-voltage signal stacking scheme for a plurality of non-volatile computing-in-memory applications is configured to compute a plurality of multi-bit input signals and a plurality of weights. A controller splits the multi-bit input signals into a plurality of input sub-groups and generates a plurality of switching signals according to the input sub-groups, and the input sub-groups are sequentially inputted to the word lines. The current-to-voltage signal stacking converter converts the bit-line current from a plurality of non-volatile memory cells into a plurality of converted voltages according to the input sub-groups and the switching signals, and the current-to-voltage signal stacking converter stacks the converted voltages to form an output voltage. The output voltage is corresponding to a sum of a plurality of multiplication values which are equal to the multi-bit input signals multiplied by the weights.

A memory unit with an asymmetric group-modulated input scheme and a current-to-voltage signal stacking scheme for a plurality of non-volatile computing-in-memory applications is configured to compute a plurality of multi-bit input signals and a plurality of weights. A controller splits the multi-bit input signals into a plurality of input sub-groups and generates a plurality of switching signals according to the input sub-groups, and the input sub-groups are sequentially inputted to the word lines. The current-to-voltage signal stacking converter converts the bit-line current from a plurality of non-volatile memory cells into a plurality of converted voltages according to the input sub-groups and the switching signals, and the current-to-voltage signal stacking converter stacks the converted voltages to form an output voltage. The output voltage is corresponding to a sum of a plurality of multiplication values which are equal to the multi-bit input signals multiplied by the weights.

Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor.

An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.

A product-sum operation device includes a product operator, a sum operator, and a malfunction determiner. The product operator includes a plurality of product operation elements (10AA) to (10AC), and each of the plurality of product operation elements (10AA) to (10AC) is a resistance change element. The sum operator includes an output detector that detects the sum of outputs from the plurality of product operation elements (10AA) to (10AC). The malfunction determiner determines that a malfunction has occurred when the sum detected by the output detector exceeds a specified value. The specified value is a value equal to or greater than a maximum value of the sum that can be detected by the output detector when the plurality of product operation elements (10AA) to (10AC) all operate normally.

Programmable interposers for connecting integrated circuits, methods for programming programmable interposers, and integrated circuit packaging are provided. The programmable interposers are electrically reconfigurable to allow custom system-in-package (SiP) operation and configuration, field configurability, and functional obfuscation for secure integrated circuits fabricated in non-trusted environments. The programmable interposer includes, in one implementation, an interposer substrate and a programmable metallization cell (PMC) switch. The PMC switch is formed on the interposer substrate and is coupled between a signal input and a signal output. The PMC switch is electrically configurable between a high resistance state and a low resistance state.