A nonvolatile memory device includes a memory block including a plurality of cell strings each of which includes memory cells electrically coupled with word lines stacked over a substrate; a plurality of sub common sources electrically coupled to one ends of the cell strings; and a plurality of bit lines electrically coupled to the other ends of the cell strings, wherein the memory block includes sub blocks respectively corresponding to the sub common sources, and cell strings electrically coupled to the same bit line among the cell strings are included in the same sub block.

Efficient data path architecture for flash devices requiring multi-pass programming utilizes an external memory as an intermediate buffer to store the encoded data used for a first pass programming of the flash device. The stored encoded data can be read from the external memory for subsequent passes programming instead of fetching the data from an on-chip memory, which stores the data received from a host system. Thus, the on-chip memory can be made available to speed up the next data transfer from the host system.

Embodiments include a system for facilitating data storage. During operation, the system receives a request to write data associated with a logical block address (LBA), wherein the LBA indicates a die to which to write the data and includes a sub-LBA which is used as an index for a mapping table stored on the die. The system assigns, based on the LBA, a physical block address (PBA) which indicates the die and includes a sub-PBA which indicates a first physical location in a block of the die at which the data is to be stored. The system stores, in the mapping table based on the sub-LBA, the PBA. The system writes the PBA and the data to the block based on the PBA.

A multi-time programmable memory cell has a differential multi-time programmable memory cell and a second-level latch cell. The differential multi-time programmable memory cell provides a first balance signal and a second balance signal, and the second-level latch cell receives the first balance signal and the second balance signal and provides an output signal according to the first balance signal and the second balance signal based on a first latch control signal and a second latch control signal.

Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more processors. The system can include a memory controller comprising logic to create a reserved memory region in a system physical address (SPA) map. The memory controller can comprise logic to detect when the one or more processors are brought online. The memory controller can comprise logic to map the memory associated with the one or more processors that are brought online to the reserved memory region in the SPA map.

Non-Volatile Static Random Access Memory (NVSRAM) cell devices applying only one single non-volatile element embedded in a conventional Static Random Access Memory (SRAM) cell are disclosed. The NVSRAM cell devices can be integrated into a compact cell array. The NVSRAM devices of the invention have a read/write speed of a conventional SRAM and non-volatile property of a non-volatile memory cell. The methods of operations for the NVSRAM devices of the invention are also disclosed.

An integrated structure includes a first MOS transistor with a first controllable gate region overlying a first gate dielectric and a second MOS transistor neighboring the first MOS transistor and having a second controllable gate region overlying the first gate dielectric. A common conductive region overlies the first and second gate regions and is separated therefrom by a second gate dielectric. The common conductive region includes a continuous element located over a portion of the first and second gate regions and a branch extending downward from the continuous element toward the substrate as far as the first gate dielectric. The branch located between the first and second gate regions.

Apparatuses and methods of pulse shaping a pulse signal for programming and erasing a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory cell are described. In one method a pulse shape of a pulse signal is controlled to include four or more phases for programming or erasing a SONOS memory cell. A write cycle is performed to program or erase the SONOS memory with the pulse signal with the four or more phases.

A semiconductor structure includes first and second source/drain region disposed in a semiconductor body and spaced from each other by a channel region. A gate electrode overlies the channel region and a capacitor electrode is disposed between the gate electrode and the channel region. A first gate dielectric is disposed between the gate electrode and the capacitor electrode and a second gate dielectric disposed between the capacitor electrode and the channel region. A first electrically conductive contact region is in electrical contact with the gate electrode and a second electrically conductive contact region in electrical contact with the capacitor electrode. The first and second contact regions are electrically isolated from one another.

A first switch transistor and a second switch transistor are turned on concurrently. Thereby a first ReRAM is electrically connected to a first storage node, and a second ReRAM is electrically connected to a second storage node. Complementary SRAM data stored in an SRAM is programmed into a non-volatile memory section of a first memory cell and a second memory cell. One of the first switch transistor and the second switch transistor is turned on to electrically connect only the first ReRAM to the first storage node or to electrically connect only the second ReRAM to the second storage node. Hence, the first memory cell or the second memory cell functions as an independent-type cell in accordance with usage. Data is programmed separately into the first memory cell M1a or the second memory cell M1b. Thus memory capacity is increased.