The present description concerns a memory device (200) including a non-volatile memory circuit (101); a buffer memory circuit (203) comprising a volatile memory circuit (221); an input-output circuit (105); a first data link (104) coupling the non-volatile memory circuit (101) to the buffer memory circuit (203); a second data link (106) coupling the buffer memory circuit (203) to the input-output circuit (105); and a control circuit (225), wherein the buffer memory circuit (203) is adapted to implementing calculations having as operands data stored in the volatile memory circuit (221).

A static random access memory including at least one memory cell is provided. The memory cell includes a first inverter, a second inverter, a first pass gate transistor, a second pass gate transistor, a first non-volatile memory, and a second non-volatile memory. The first inverter and the second inverter are coupled to each other. The first pass gate transistor is coupled between the first inverter and the first bit line. The second pass gate transistor is coupled between the second inverter and the second bit line. The first non-volatile memory is coupled between the first pass gate transistor and the first bit line. The second non-volatile memory is coupled between the second pass gate transistor and the second bit line.

The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. By restricting the host to have a minimum write size, the data transfer speed to RAM2, RAM1, and the storage unit can be optimized. A temporary buffer is utilized within the RAM1 to update parity data for the corresponding commands. The parity data is updated in the RAM1 and written to the RAM2 in the corresponding zone. The parity data may be copied from the RAM2 to the RAM1 to update the parity data in the temporary buffer when commands are received to write data to corresponding zones. As the parity data is updated, the corresponding command is simultaneously written to the corresponding zone.

A novel memory device is provided. The memory device including a plurality of memory cells arranged in a matrix, and each of the memory cells includes a transistor and a capacitor. The transistor includes a first gate and a second gate, which include a region where they overlap with each other with a semiconductor layer therebetween. The memory device has a function of operating in a “writing mode”, a “reading mode”, a “refresh mode”, and an “NV mode”. In the “refresh mode”, data retained in the memory cell is read, and then the read data is written to the memory cell again for first time. In the “NV mode”, data retained in the memory cell is read, the read data is written to the memory cell again for second time, and then a potential at which the transistor is turned off is supplied to the second gate. The “NV mode” operation enables data to be stored for a long time even when power supply to the memory cell is stopped. The memory cell can store multilevel data.

Memory devices might include a controller for access of an array of memory cells and a differential storage device comprising a pair of gate-connected non-volatile memory cells, wherein the controller is configured to cause the memory device to obtain information indicative of a data value stored in a particular memory cell of the array of memory cells, program additional data to the particular memory cell, determine if a power loss to the memory device is indicated while programming the additional data to the particular memory cell, and, if a power loss to the memory device is indicated, selectively program one memory cell of the pair of gate-connected non-volatile memory cells responsive to the information indicative of the data value stored in the particular memory cell.

Technologies for a multi-bit non-volatile dynamic random access memory (nvDRAM) device, which may include a DRAM array having a plurality of DRAM cells with single or dual transistor implementation and a non-volatile memory (NVM) array having a plurality of NVM cells with single or dual transistor implementations, where the DRAM array and the NVM array are arranged by rows of word lines and columns of bit lines. The nvDRAM device may also include one or more of isolation devices coupled between the DRAM array and the NVM array and configured to control connection between the dynamic random access bit lines (BLs) and the non-volatile BLs. The word lines run horizontally and may enable to select one word of memory data, whereas bit lines run vertically and may be connected to storage cells of different memory address.

The present disclosure includes multifunctional memory cells. A number of embodiments include a charge transport element having an oxygen-rich silicon oxynitride material, a volatile charge storage element configured to store a first charge transported through the charge transport element, and a non-volatile charge storage element configured to store a second charge transported through the charge transport element, wherein the non-volatile charge storage element includes a gallium nitride material.

An embodiment integrated circuit comprises a memory device including at least one memory point having a volatile memory cell and a single non-volatile memory cell coupled together to a common node.

A contactless transponder includes a non-volatile static random access memory including memory points. Each memory point is formed by a volatile memory cell and a non-volatile memory cell. A protocol processing circuit receives data and stores the received data in the volatile memory cells of the memory. A write processing circuit is configured, at the end of the reception and storage of the data, to record, in a single write cycle, the data from the volatile memory cells to the non-volatile memory cells of the respective memory points.

Methods of operating memory might include storing information indicative of a data value of a digit of data stored in a particular memory cell of the memory prior to programming a subsequent digit of data to the particular memory cell, programming the subsequent digit of data to the particular memory cell, monitoring a voltage level of a supply voltage to the memory while programming the subsequent digit of data, and, if the voltage level of the supply voltage falls below a threshold while programming the subsequent digit of data and the information indicative of the data value of the digit of data has a particular logic level, causing a change in threshold voltage of one memory cell of a pair of gate-connected non-volatile memory cells, and inhibiting the other memory cell of the pair of gate-connected non-volatile memory cells from a change in threshold voltage.