Embodiments include apparatuses, methods, and systems associated with save-restore circuitry including metal-ferroelectric-metal (MFM) devices. The save-restore circuitry may be coupled to a bit node and/or bit bar node of a pair of cross-coupled inverters to save the state of the bit node and/or bit bar node when an associated circuit block transitions to a sleep state, and restore the state of the bit node and/or bit bar node when the associated circuit block transitions from the sleep state to an active state. The save-restore circuitry may be used in a flip-flop circuit, a register file circuit, and/or another suitable type of circuit. The save-restore circuitry may include a transmission gate coupled between the bit node (or bit bar node) and an internal node, and an MFM device coupled between the internal node and a plate line. Other embodiments may be described and claimed.

Technologies for various memory structures for artificial intelligence (AI) applications and methods thereof are described. An XNOR circuit along with a sense amplifier may be combined with an array (or multiple arrays) of memory such as non-volatile memory (NVM) or an NVM, SRAM combination to perform an XNOR operation on the data read from the memory. Various versions may include different connections allowing simplification of circuitry or timing. In some examples, memory array may include programmable resistor/switch device combinations, or multiple columns connected to a single XNOR+SA circuit.

A configuration memory cell includes a latch portion including a cross-coupled latch having complementary output nodes, and a programmable read-only memory (PROM) portion coupled to one of the complementary output nodes of the latch portion, the PROM portion including a programmable and erasable ReRAM device.

A semiconductor memory includes a first and a second transistor each with one of source/drain connected to a first wiring. The other of the source/drain for each of first and second transistor is connected to the gate of the other transistor. A third and a fourth transistor each have gates connected to a second wiring, one of source/drain of each connected to a third or fifth wiring, the other of the source/drain connected to the other of the source/drain of the first or second transistor. For the third transistor, a gate insulation layer includes a first ferroelectric material. For the fourth transistor, and a gate insulation layer includes a second ferroelectric material.

In one embodiment, a device is described for using ferroelectric material in a memory cell without a selector device. In another embodiment, a method of operating a ferroelectric memory cell without a selector device is described. Other embodiments are likewise described.

A semiconductor circuit according to the present disclosure includes: a first circuit that is configured to apply an inverted voltage of a voltage at a first node to a second node; a second circuit that is configured to apply an inverted voltage of a voltage at the second node to the first node; a first transistor that includes a gate, a drain, and a source, and is configured to store a threshold state; a second transistor that couples the first node to a first terminal by being turned on; a third transistor that couples a first predetermined node to the gate of the first transistor; and a driving section that controls operations of the second transistor and the third transistor, and applies a control voltage to a second terminal. The first terminal is one of the drain or the source of the first transistor. The first predetermined node is one of the first node or the second node. The second terminal is another of the drain or the source of the first transistor.

Described is an apparatus which comprises: a first access transistor controllable by a write word-line (WWL); a second access transistor controllable by a read word-line (RWL); and a ferroelectric cell coupled to the first and second access transistors, wherein the ferroelectric cell is programmable via the WWL and readable via the RWL. Described is a method which comprises: driving a WWL, coupled to a gate terminal of a first access transistor, to cause the first access transistor to turn on; and driving a WBL coupled to a source/drain terminal of the first access transistor, the driven WBL to charge or discharge a storage node coupled to the first access transistor when the first access transistor is turned on, wherein the ferroelectric cell is coupled to the storage node and programmable according to the charged or discharged storage node.

Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the I.sub.DSV.sub.G hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two I.sub.DS states at V.sub.G=0.

A random bit cell includes a latch, a voltage selector, a first non-volatile storage element, and a second non-volatile storage element. The latch has a first terminal coupled to a first local bit line, and a second terminal coupled to a second local bit line. The first non-volatile storage element has a first terminal coupled to the first local bit line, and a second terminal coupled to the voltage selector. The second non-volatile storage element has a first terminal coupled to the second local bit line, and a second terminal coupled to the voltage selector. During an initial operation, the first terminals of the first non-volatile storage element and the second non-volatile storage element are floating. During an enroll operation, the first terminals of the first non-volatile storage element and the second non-volatile storage element receive a program voltage from the voltage selector.

A memory device and an operation method thereof are provided. The memory device includes memory cells, each having a static random access memory (SRAM) cell and a non-volatile memory cell. The SRAM cell is configured to store complementary data at first and second storage nodes. The non-volatile memory cell is configured to replicate and retain the complementary data before the SRAM cell loses power supply, and to rewrite the replicated data to the first and second storage nodes of the SRAM cell after the power supply of the SRAM cell is restored.