A multilevel content addressable memory, a multilevel coding method and a multilevel searching method are provided. The multilevel coding method includes the following steps. A highest decimal value of a multilevel-bit binary data is obtained. A length of a digital string data is set as being the highest decimal value of the multilevel-bit binary data. The multilevel-bit binary data is converted into the digital string data. If a content of the multilevel-bit binary data is an exact value, a number of an indicating bit in the digital string data is the exact value.

An in-memory digital processor, Perpetual Digital Perceptron (PDP), is disclosed. The digital in-memory processor of the invention processes the input digital information according to a database of the digital content data stored/hardwired in the Content Read Only Memory (CROM) array and outputs the correspondent digital response data stored/hardwired in the Response Read Only Memory (RROM) array. The PDP is the hardwired digital in-memory processor without re-configuration capability and similar to the instinct functions of biological hardwired brains without re-shaping their neuromorphic structures from training and learning.

A ternary content addressable memory (TCAM) semiconductor device includes a first and second data storage portions each connected to a bit line. The first data storage portion is connected to a first word line, and to a first and third group of in series transistors. The second data storage portion is connected to a second word line, and to a second and fourth group of in series transistors. The first group and second group of in series transistors are each connected to a first match line. The first group is connected to a first search line bar, and the second group is connected to a first search line. A third and fourth group of in series transistors are each connected to a second match line. The third group is connected to a second search line, and the fourth group is connected to a second search line bar.

Disclosed is a content addressable memory device including a memory cell array including a plurality of memory cells, each of which has a ferroelectric tunnel field effect transistor (FeTFET), and a match amplifier connected to the plurality of memory cells through a plurality of match lines. The FeTFET includes a first doped region including a first conductivity type, a second doped region including a second conductivity type different from the first conductivity type, a channel region formed between the first doped region and the second doped region, and a gate formed on the channel region and including a ferroelectric layer.

A memory cell for an analog content-addressable memory is provided. The memory cell includes an N-type transistor, a P-type transistor, and a current control circuit. The gate of the N-type transistor is configured to receive a first input signal. The gate of the P-type transistor is configured to receive a second input signal. The current control circuit is coupled to at least one of the N-type transistor and the P-type transistor. The current control circuit is configured to generate at least one passing current. When the input voltages of the first input signal and the second input signal are within a matching range, the N-type transistor and the P-type transistor are turned on, and the passing current is substantially a fixed current value. The matching range is related to the threshold voltages of the N-type transistor and the P-type transistor, and the fixed current value.

A search pattern is generated based on an input search word comprising a first sequence of bits. The search pattern comprises a representation of the input search word and a representation of an inverse of the input search word. The search pattern is provided as input to search lines of a ternary content-addressable memory (TCAM) block. A subset of the search lines is set to a logical high state based on a first portion of the input search word being designated as don't-care bits. The search pattern causes at least one string in the CAM block to be conductive and provide a signal in response to a data entry stored on the string comprising a second portion of the input search word that excludes the don't-care bits. A location of the data entry is determined and output.

A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data .

This application relates to the field of storage technologies and discloses a content addressable memory, a data processing method, and a network device, to resolve a problem that an existing CAM has a relatively large area, and consumes relatively large power. The CAM includes bit units of M rows and N columns, each bit unit includes a first FeFET and a second FeFET, a source of the first FeFET is connected to a drain of the second FeFET, a source of the second FeFET is grounded, bit cells of a same column correspond to a same match line, and a drain of a first FeFET in each bit cell of a same column is connected to a match line corresponding to the column. Bit cells of a same row correspond to a same first bit line and a same second bit line, a gate of a first FeFET in each bit cell of a same row is connected to a first bit line corresponding to the row, and a gate of a second FeFET in each bit cell of a same row is connected to a second bit line corresponding to the row. The CAM may be applied to a network device such as a router.

A content addressable memory based on a self-rectifying ferroelectric tunnel junction element comprises: a cell array unit having a plurality of TCAM cells, each comprising two self-rectifying ferroelectric tunnel junction elements (SR-FTJ) connected between a corresponding match line of a plurality of match lines extending in a first direction and a corresponding bit line pair of a plurality of bit line pairs extending in a second direction; a precharge unit precharging a corresponding match line of the plurality of match lines to a power supply voltage level in response to a precharge signal; and a data input/output unit having a plurality of access transistor pairs electrically connecting or disconnecting a corresponding bit line pair among the plurality of bit line pairs and a source line, in response to a voltage applied through a corresponding search line pair among a plurality of search line pairs according to data to be written or searched.

A memory system includes a memory device comprising a content addressable memory (CAM) block comprising a plurality of key tables each storing a respective plurality of stored search keys. The memory system further includes a processing device that receives, from a requestor, an input search key and an indication of one of the plurality of key tables and identifies a match between the input search key and one of the plurality of stored search keys in the one of the plurality of key tables. The one of the plurality of stored search keys has an associated offset value indicating a location in a sorted string table (SSTable) corresponding to the one of the plurality of key tables. The processing device further reads the offset value from the one of the plurality of key tables and returns, to the requestor, the offset value read from the one of the plurality of key tables. The requestor can retrieve, from the location in the SSTable, data representing a value associated with the input search key.