A semiconductor device includes a one-time programmable (OTP) memory including a key program area and a plurality of key protection setting areas. A key is stored in the key program area, and a plurality of setting values that protect the key stored in the key program area are programmed in the key protection setting areas. The semiconductor device further includes a key register and a key protection control logic circuit. The key register is configured to load the key stored in the OTP memory. The key is accessible to secure software when the key is loaded into the key register. The key protection control logic circuit is configured to load the key stored in the OTP memory into the key register based on the setting values programmed in the key protection setting areas of the OTP memory.

According to one embodiment, a semiconductor memory device includes a MOS transistor and a drive circuit. The MOS transistor has a gate and a gate insulating film. The drive circuit is coupled to the gate and supplies a first voltage that destroys the gate insulating film or a second voltage lower than the first voltage. The drive circuit applies the first voltage to the gate in a first write to the MOS transistor, and applies the second voltage to the gate in a second write to the MOS transistor.

A state detection circuit for an anti-fuse memory cell includes: amplifier, having first input terminal connected with first reference voltage, second input terminal connected with first node and output terminal connected with second node; anti-fuse memory cell array, including anti-fuse memory cell sub-arrays, bit lines of sub-arrays are connected with first node, word lines of sub-arrays are connected with controller and each sub-array includes anti-fuse memory cells; first switch element, having first terminal connected with power supply, second terminal connected with first node and control terminal connected with second node; second switch element, having first terminal connected with power supply, second terminal connected with third node and control terminal connected with second node; third switch element, having first terminal connected with third node, grounded second terminal and control terminal connected with controller; and comparator, having first and second input terminals connected with third node and second reference voltage respectively.

An integrated circuit (IC) device configured for multiple return material authorizations (RMAs) is provided. The IC device includes an asset and a return material authorization (RMA) counter fuse including a first fuse, a second fuse, and a third fuse. The IC device enters an RMA state in response to blowing the first fuse, a second state in response to blowing the second fuse, and the RMA state in response to blowing the third fuse.

Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, including both non-volatile and volatile memories. The memory circuitry employs an antifuse scheme that includes an array of 1T bitcells, wherein each bitcell effectively contains one gate or transistor-like device that provides both an antifuse element and a selector device for that bitcell. In particular, the bitcell device has asymmetric trench-based source/drain contacts such that one contact forms a capacitor in conjunction with the spacer and gate metal, and the other contact forms a diode in conjunction with a doped diffusion area and the gate metal. The capacitor serves as the antifuse element of the bitcell, and can be programmed by breaking down the spacer. The diode effectively provides a Schottky junction that serves as a selector device which can eliminate program and read disturbs from bitcells sharing the same bitline/wordline.

A semiconductor memory device and an operation method thereof that can accurately read setting information from a memory cell array when a power supply is turned on are provided. The flash memory includes a memory cell array, a detecting portion, a ROM and a control portion. The detecting portion detects that the power supply is turned on. The ROM stores at least a code for performing a reading operation of the memory cell array and stores a special code in a specific address. The control portion controls the reading of the ROM. When the detecting portion detects the power-on of the power supply, the control portion reads the special code from the ROM and determines whether the read special code is correct or not, reads the code if the determination is correct and again reads the special code if the determination is incorrect.

Certain aspects of the present disclosure are directed to methods and apparatus for programming a device having one or more programmable circuits to implement, for example, a machine learning model. One example apparatus generally includes a plurality of word lines, a plurality of bit lines, and an array of programmable circuits. Each programmable circuit is coupled to a corresponding word line in the plurality of word lines and to a corresponding bit line in the plurality of bit lines and comprises: a main resistor coupled between the corresponding word line and the corresponding bit line, an auxiliary resistor, a fuse coupled in series with the auxiliary resistor, wherein the auxiliary resistor and the fuse are coupled between the corresponding word line and the corresponding bit line, and a programming circuit configured to selectively blow the fuse.

The present invention discloses a processor for enhancing network security, i.e. a three-dimensional (3-D) security processor. It is a monolithic integrated circuit comprising a plurality of storage-processing units (SPU). Each SPU comprises at least a three-dimensional memory (3D-M) array for permanently storing rule/virus patterns and a pattern-processing circuit for performing pattern processing on an incoming network packet against said rule/virus patterns. The 3D-M array is stacked above the pattern-processing circuit.

A method for programming a one-time programmable structure is disclosed. The method comprises producing an electrical circuit having the one-time programmable structure. The method furthermore comprises severing the one-time programmable structure by etching the one-time programmable structure in a separating region.

To achieve a better overall performance, a preferred pattern processor offsets large latency with massive parallelism. It comprises a plurality of storage-processing units (SPU's), each of which comprises a single pattern-processing circuit, at least a three-dimensional memory (3D-M) array and a plurality of inter-storage-processor (ISP) connections. The ISP-connections do not penetrate through any semiconductor substrate.