The present invention discloses a processor for enhancing computer security, i.e. a three-dimensional (3-D) security processor. It is a monolithic integrated circuit comprising a plurality of storage-processing units (SPU). Each SPU comprises at least a three-dimensional memory (3D-M) array for permanently storing virus patterns and a pattern-processing circuit for performing pattern processing on a scanned computer data against said virus patterns. The 3D-M array is stacked above the pattern-processing circuit.

The present disclosure relates to method and system of implementing one wire programmable circuit by using the same terminal OUT as both main circuit output terminal and the digital I/O interfacing terminal of the circuit. The present invention overcomes the shortcoming of prior arts and does not require the circuit to be powered down first and then powered up again each time the circuit is switched between interfacing mode (read/write/program OTP) and the normal output mode, therefore shorten the time of interfacing with the OTP as well as simplified the interfacing system used to read/write/program the OTP. The present invention also enables the possibility to put the no longer required system clock into sleeping mode after the OTP has been programmed, and has the advantages of reducing system power consumption as well as system noise due to the existing of digital clock.

A fuse array and a memory device are provided in the invention. The fuse array includes a plurality of fuses and a plurality of first D flip-flops. The fuses are configured to generate a plurality of data signals. Each of the first D flip-flops is respectively coupled to one corresponding fuse of the fuses to receive the data signal from the corresponding fuse and the first D flip-flops transmit a clock signal and the data signal to a plurality of second D flip-flops comprised in a plurality of memory cells. The first D flip-flops are connected in series and the second D flip-flops are connected in series.

A semiconductor memory device and an operation method thereof that can accurately read setting information from a memory cell array when a power supply is turned on are provided. The flash memory includes a memory cell array, a detecting portion, a ROM and a control portion. The detecting portion detects that the power supply is turned on. The ROM stores at least a code for performing a reading operation of the memory cell array and stores a special code in a specific address. The control portion controls the reading of the ROM. When the detecting portion detects the power-on of the power supply, the control portion reads the special code from the ROM and determines whether the read special code is correct or not, reads the code if the determination is correct and again reads the special code if the determination is incorrect.

A semiconductor device includes a one-time programmable (OTP) memory including a key program area and a plurality of key protection setting areas. A key is stored in the key program area, and a plurality of setting values that protect the key stored in the key program area are programmed in the key protection setting areas. The semiconductor device further includes a key register and a key protection control logic circuit. The key register is configured to load the key stored in the OTP memory. The key is accessible to secure software when the key is loaded into the key register. The key protection control logic circuit is configured to load the key stored in the OTP memory into the key register based on the setting values programmed in the key protection setting areas of the OTP memory.

A multi-level distributed pattern processor comprises a plurality of storage-processing units (SPU's). Each of the SPU's comprises at least a non-volatile memory (NVM) array and a pattern-processing circuit. The NVM array and the pattern-processing circuit are disposed on different physical levels.

A timing of an execution of a command in a memory device can be affected delay elements. The delay elements of a unit of delay elements can cause variable delays of the command paths. The delay elements can be activated based on settings stored in a fuse array of a memory device. The delay elements can be used to change a timing of current draw of the memory devices.

A method of manufacturing an electronic circuit comprises: providing an electronic circuit having a first configuration in which the circuit comprises a resistive element having a first resistance, and irradiating at least a part of the resistive element with electromagnetic radiation to change the resistance of the resistive element from the first resistance to a second resistance, the second resistance being lower than the first resistance. A method of storing data comprises: receiving a piece of data to be stored; determining a number according to the data; and irradiating at least part of a resistive element with that number of pulses of electromagnetic radiation to change a resistance of the resistive element from a first resistance to a second resistance, the second resistance being lower than the first resistance. A difference between the first resistance and the second resistance is dependent on the number. Corresponding circuits and data storage systems are disclosed.

The present invention discloses a configurable computing array based on three-dimensional printed memory (3D-P). It comprises an array of configurable computing elements, an array of configurable logic elements and a plurality of configurable interconnects. Each configurable computing element can selectively realize a basic function in a math library. It comprises a plurality of 3D-P arrays storing the look-up tables (LUT) for the basic functions in the math library.

A method of manufacturing an electronic circuit comprises: providing an electronic circuit having a first configuration in which the circuit comprises a resistive element having a first resistance, and irradiating at least a part of the resistive element with electromagnetic radiation to change the resistance of the resistive element from the first resistance to a second resistance, the second resistance being lower than the first resistance. A method of storing data comprises: receiving a piece of data to be stored; determining a number according to the data; and irradiating at least part of a resistive element with that number of pulses of electromagnetic radiation to change a resistance of the resistive element from a first resistance to a second resistance, the second resistance being lower than the first resistance. A difference between the first resistance and the second resistance is dependent on the number. Corresponding circuits and data storage systems are disclosed.