A device, including: an unsecure non-volatile memory; a secure device including: a processor; and a secure non-volatile memory; wherein the secure device is configured to: calculate a TMC value from an offset and a base value; store a TMC version value in the secure non-volatile memory and the insecure non-volatile memory, wherein the TMC version value is updated when TMC value is incremented the first time after the secure device is powered up; store the base value in the unsecure non-volatile memory; store the offset value in the unsecure non-volatile memory when the secure device is in a system power down state; store the offset value in the secure non-volatile memory when the secure device is in a rescue state; and store a TMC link value in the unsecure memory, wherein the TMC link value is based upon the base value and TMC version value stored in the unsecure memory.

A method includes: reading a plurality of words from a one-time program (OTP) memory of a processing chip, wherein each of the words includes secure data for the chip and bits corresponding to a check pattern; comparing the bits corresponding to the check pattern to a preprogrammed check pattern; detecting an error based on comparing the bits corresponding to the check pattern to the preprogrammed check pattern; and performing an action by the processing chip in response to detecting the error.

A semiconductor device for a one-time programmable (OTP) memory according to some examples of the disclosure includes a gate, a dielectric region below the gate, a source terminal below the dielectric region and offset to one side, a drain terminal below the dielectric region and offset to an opposite side from the source terminal, a drain side charge trap in the dielectric region capable of programming the semiconductor device, and a source side charge trap in the dielectric region opposite the drain side charge trap and capable of programming the semiconductor device.

A semiconductor device for a one-time programmable (OTP) memory according to some examples of the disclosure includes a gate, a dielectric region below the gate, a source terminal below the dielectric region and offset to one side, a drain terminal below the dielectric region and offset to an opposite side from the source terminal, a drain side charge trap in the dielectric region capable of programming the semiconductor device, and a source side charge trap in the dielectric region opposite the drain side charge trap and capable of programming the semiconductor device.

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuses. At least one portion of the electrical fuse can have at least one extended area to accelerate programming. An extended area is an extension of the fuse element beyond contact or via longer than required by design rules. The extended area also has reduced or substantially no current flowing through. The program selector can be at least one MOS. The OTP device can have the at least one OTP element coupled to at least one diode in a memory cell.

A memory device includes: a memory array comprising a plurality of bit cells arranged along a plurality of rows and along a plurality of columns, respectively; a plurality of row circuits respectively arranged along the plurality of rows; a plurality of column circuits respectively arranged along the plurality of columns; and a control logic circuit coupled to the memory array, and configured to determine respective locations of a first plurality of diagonal bit cells of the memory array for testing the pluralities of the row and column circuits.

A memory system comprising: a memory cell. The memory cell comprising a poly-fuse-resistor; and a bipolar junction transistor having a collector-emitter channel and a base-terminal. The collector-emitter channel of the bipolar junction transistor is connected in series with the poly-fuse resistor between a supply-voltage-terminal and a ground-terminal. The base-terminal of the bipolar junction transistor is configured to receive a transistor-control-signal to selectively control a current flow through the poly-fuse-resistor.

Gate oxide breakdown in the programming element of an OTP (One-Time Programmable) memory cell can vary widely. The resulting large variations in the conductivity of the programmed memory cells in an OTP memory cell array is used for a PUF (Physically Unclonable Function). A method of obtaining a PUF value from an OTP memory cell array is described.

A method is proposed for storing bits in memory cells of a memory, wherein in two successive write operations first and second wits are written to identical memory cells at an identical address, without the memory cells being erased after the first write operation, wherein first check bits are stored in further first memory cells and second check bits are stored in further second memory cells. A corresponding device is furthermore specified.

Both rewriting and error correction are technologies usable for non-volatile memories, such as flash memories. A coding scheme is disclosed herein that combines rewriting and error correction for the write-once memory model. In some embodiments, code construction is based on polar codes, and supports any number of rewrites and corrects a substantial number of errors. The code may be analyzed for a binary symmetric channel. The results can be extended to multi-level cells and more general noise models.