Error correction using WOM codes

Abstract

A method is proposed for storing bits in memory cells of a memory, wherein in two successive write operations first and second wits are written to identical memory cells at an identical address, without the memory cells being erased after the first write operation, wherein first check bits are stored in further first memory cells and second check bits are stored in further second memory cells. A corresponding device is furthermore specified.

Claims

1. A method for storing bits in memory cells of a memory, comprising: writing first wits and second wits to identical memory cells at an identical address of the memory via two successive write operations, without the memory cells being erased after a first write operation of the two successive write operations; and storing first check bits in further first memory cells and second check bits in further second memory cells, wherein the number of first check bits is less than the number of the first wits, and wherein the memory cells are physical memory cells susceptible to at least one of transient memory errors or permanent memory errors.

2. The method as claimed in claim 1, wherein a first code word of a first error code is determined on the basis of the first wits and the first check bits, wherein a second code word of a second error code is determined on the basis of the second wits and the second check bits.

3. The method as claimed in claim 1, wherein the first wits and the second wits are determined on the basis of useful data bits by means of at least one WOM code.

4. The method as claimed in claim 3, wherein at least one inversion bit is added to the useful data bits, wherein a subset of useful data bits is assigned to the at least one inversion bit.

5. The method as claimed in claim 4, wherein the at least one inversion bit assumes a first value if the useful data bits assigned to the inversion bit are not inverted, and the inversion bit assumes a second value different therefrom if the useful data bits assigned to the inversion bit are inverted.

6. The method as claimed in claim 5, wherein the respective wits are formed using the useful data bits and the inversion bit, wherein the useful data bits assigned to the at least one inversion bit are not inverted if the inversion bit has the first value, and wherein the useful data bits assigned to the at least one inversion bit are inverted if the inversion bit has the second value.

7. The method as claimed in claim 4, wherein in the first write operation the first check bits are determined such that the first wits determined from the useful data bits and the at least one inversion bit and the first check bits are bits of the first code word, and wherein in the second write operation at the same address the second check bits are determined such that the second wits determined from the useful data bits and the at least one inversion bit and the second check bits are bits of the second code word.

8. The method as claimed in claim 4, wherein the useful data bits assigned to the at least one inversion bit are all useful data bits.

9. The method as claimed in claim 3, wherein before the write operation, in memory cells to be addressed, the data stored there are read out, wherein the data read out are compared with the data to be stored, wherein the data to be stored are inverted if the data to be stored cannot be written to the memory in an error-free manner, wherein the first wits or the second wits are determined on the basis of the inverted data by means of the at least one WOM code and are stored in the memory cells.

10. The method as claimed in claim 3, wherein the first wits coded by means of the at least one WOM code are different than the second wits coded by means of the at least one WOM code.

11. The method as claimed in claim 3, wherein at least one memory cell of the memory is not completely erased before the first writing, wherein the first wits and the second wits are coded by means of the at least one WOM code on the basis of the at least one not completely erased memory cell.

12. The method as claimed in claim 3, wherein the first wits and the second wits are organized in each case as blocks, wherein two different codings are assigned to each occupancy of the bits of one of the blocks of the first wits by the at least one WOM code.

13. The method as claimed in claim 1, wherein the number of second check bits is less than the number of second wits.

14. The method as claimed in claim 1, wherein the first error code is an error detecting code and/or an error correcting code, and wherein the second error code is an error detecting code and/or an error correcting code.

15. The method as claimed in claim 1, wherein the first error code is a code having a code distance of greater than or equal to three.

16. The method as claimed in claim 1, wherein the second error code is a code having a code distance of greater than or equal to three.

17. The method as claimed in claim 1, wherein the further first memory cells and the further second memory cells are different than one another.

18. The method as claimed in claim 1, wherein if no error occurs, the first wits and the first check bits are a proper subset of bits of the first code word, or the second wits and the second check bits are a proper subset of bits of the second code word, or the first wits and the first check bits are a proper subset of the bits of the first code word and also the second wits and the second check bits are a proper subset of the bits of the second code word.

19. The method as claimed in claim 1, wherein the length of the first error code is greater than the number of first wits and first check bits, and wherein the length of the second error code is greater than the number of second wits and second check bits.

20. The method as claimed in claim 1, wherein the first code word of the first error code is determined on the basis of the first wits, the first check bits and first additional bits, and wherein the second code word of the second error code is determined on the basis of the second wits, the second check bits and second additional bits.

21. The method as claimed in claim 20, wherein when writing to the memory and/or when reading from the memory, the first wits, the first check bits and the first additional bits form the first code word and the second wits, the second check bits and the second additional bits form the second code word.

22. The method as claimed in claim 20, wherein the first additional bits and/or the second additional bits are based in each case at least on one of the following items of information: address information, address information concerning a write address or a read address, information derived from address information, identifier information, password information, inversion information.

23. The method as claimed in claim 20, wherein an error in the first additional bits is detected and/or corrected, and/or wherein an error in the second additional bits is detected and/or corrected.

24. The method as claimed in claim 1, wherein a marking is stored in the first further memory cells provided that the second check bits are stored in the further second memory cells.

25. The method as claimed in claim 24, wherein the marking is a bit sequence that does not constitute a valid bit sequence of the first check bits.

26. The method as claimed in claim 1, wherein a partial area of the memory is erased which comprises the address to which a write operation was applied if the first or second wits to be stored at d.sub.N positions do not have the desired state after the write operation and/or if the first check bits or the second check bits at d.sub.P positions do not have the desired state after the write operation.

27. The method as claimed in claim 1, wherein a second partial area of the memory is used if the first or second wits to be stored at d.sub.N positions do not have the desired state after the write operation to a first partial area and/or if the first check bits or the second check bits at d.sub.P positions do not have the desired state after the write operation.

28. The method as claimed in claim 26, wherein the partial area is erased or the second partial area is used instead of the first partial area if it holds true that d.sub.N+d.sub.PS.sub.2, wherein S.sub.2 is a threshold value for which S.sub.20 holds true.

29. The method as claimed in claim 1, wherein the further first memory cells and the further second memory cells are different than one another if the first check bits cannot be overwritten by the second check bits without a predefined number of erroneous memory cells occurring.

30. The method as claimed in claim 29, wherein the predefined number of erroneous memory cells is greater than or equal to zero.

31. The method as claimed in claim 1, wherein the number of first check bits is greater than one, and wherein the number of second check bits is greater than one.

32. The method as claimed in claim 1, wherein the memory comprises at least one of the following types of memories: a volatile memory; a non-volatile memory.

33. A device for storing bits in memory cells of a memory comprising: a processing unit configured to: write first wits and second wits to identical memory cells at an identical address of the memory via that in two successive write operations, without the memory cells being erased after a first write operation of the two successive write operations; and store first check bits in further first memory cells and second check bits in further second memory cells, wherein the number of first check bits is less than the number of the first wits, and wherein the memory cells are physical memory cells susceptible to at least one of transient memory errors or permanent memory errors.

34. The device as claimed in claim 33, wherein the processing unit is further configured to: determine a first code word of a first error code is determined on the basis of the first wits and the first check bits; and determine a second code word of a second error code on the basis of the second wits and the second check bits.

35. The device as claimed in claim 33, wherein the device comprises the further first memory cells and the further second memory cells.

36. The device as claimed in claim 33, wherein at least one of the further first memory cells or the further second memory cells comprises at least one of a non-volatile memory or a volatile memory.

37. The method as claimed in claim 1, wherein the memory is a flash memory.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1a shows completely erased memory cells at an address 10011,

(2) FIG. 1b shows an occupancy of the memory cells from FIG. 1a after a first write operation using a WOM code,

(3) FIG. 1c shows an occupancy of the memory cells from FIG. 1a after a second write operation using the same WOM code as in FIG. 1b,

(4) FIG. 2 shows memory cells comprising 6 memory cells for storing wits, comprising 7 memory cells for storing 7 check bits of a first code C.sup.1 in a first write operation, and comprising 6 memory cells for storing 6 check bits of a second code C.sup.2 in a second write operation,

(5) FIG. 3 shows occupancies of memory cells with the addresses 1010 and 1011, wherein the address bits are included in the formation of the check bits,

(6) FIG. 4 shows occupancies of memory cells with the address 1010 after the first write operation, wherein the parity of the address bits is incorporated in the formation of the check bits,

(7) FIG. 5a shows occupancies of memory cells after an incomplete erasure operation,

(8) FIG. 5b shows occupancies of the memory cells from FIG. 5a after a first write operation, wherein the useful data bits and an inversion bit were inverted before the formation of wits,

(9) FIG. 6 shows one exemplary circuit arrangement for encoding,

(10) FIG. 7 shows one exemplary circuit arrangement for decoding,

(11) FIG. 8 shows one exemplary circuit arrangement in which a multiplexer is controlled depending on a marking signal of the first check bits.

DETAILED DESCRIPTION

(12) Error Detecting, Error Correcting Codes

(13) An error detecting and/or error correcting code is also designated herein as error code.

(14) An error code C of length n having k information bits can be described by its generator matrix G or its H-matrix H. In this case, the generator matrix is a (k, n) matrix and the H-matrix is an (nk, n) matrix. It is possible to determine k information bits u.sub.1, . . . , u.sub.k in n bits of a code word v=v.sub.1, . . . , v.sub.n in accordance with
v=v.sub.1, . . . ,v.sub.n=[u.sub.1, . . . ,u.sub.k].Math.G=u.Math.G

(15) If the generator matrix and the H-matrix are in systematic form, it holds true that
G=(I.sub.k,P.sub.k,m)
and
H=(P.sub.m,k.sup.T,I.sub.m)
where m=nk. In this case
I.sub.k is the k-dimensional identity matrix,
I.sub.m is the m-dimensional identity matrix,
P.sub.k,m is the (k, m) parity matrix, and
P.sub.m,k.sup.T is the transposed parity matrix obtained by interchanging rows and columns from the parity matrix P.sub.k,m.

(16) In the case of a systematic code, a possible H-matrix arises directly from the G-matrix. Furthermore, for systematic codes it holds true that:
v=u,c
v=u.Math.G
where
u=u.sub.1, . . . ,u.sub.k and c=c.sub.1, . . . ,c.sub.m.
Check bits c.sub.1, . . . , c.sub.m
c.sub.1, . . . ,c.sub.m=[u.sub.1, . . . ,u.sub.k].Math.P.sub.k,m
are added to the information bits u.sub.1, . . . , u.sub.k.

(17) A word v=v.sub.1, . . . , v.sub.n is a code word of the code C if

(18) $0 | = H .Math. v^{T} or \underset{m}{\underset{}{0, .Math., 0}} = v .Math. H^{T}$
wherein 0| here denotes an m-dimensional column vector.

(19) If a matrix, here the matrix H, is multiplied from the left by a vector, here the vector v, then the vector v is a row vector. If a matrix, here the matrix H, is multiplied from the right by a vector v.sup.T, then the vector v.sup.T is a column vector, wherein the vector v.sup.T is the transposed column vector of the row vector v.

(20) If
v=v.sub.1, . . . ,v.sub.n=ve=v.sub.1e.sub.1, . . . ,v.sub.ne.sub.n
is a word that emerged from a code word v=v.sub.1, . . . , v.sub.n as a result of errors, e=e.sub.1, . . . , e.sub.n is designated as error vector.

(21) If it holds true that e.sub.i=1 for i{1, . . . , n}, then v.sub.i=v.sub.i1=v.sub.i, and the i-th component v.sub.i is erroneous. If it holds true that e.sub.i=0 for i{1, . . . , n}, then v.sub.i=v.sub.i0=v.sub.i, and the i-th component v.sub.i is correct.

(22) If the error vector e has a number of q components that are equal to 1, a q-bit error is present.

(23) An error syndrome s=s.sub.1, . . . , s.sub.m is determined by
s.sup.T=H.Math.v.sup.T=H.Math.e.sup.T
and s.sup.T is equal to 0| if the word v is a code word.

(24) If the code C is a -bit error detecting code, then s.sup.T0| for all 1, . . . , -bit errors.

(25) If the code C is a t-bit error correcting code, then s.sup.T is different for all different 1, . . . , t-bit errors.

(26) The Hamming distance d(v.sup.1,v.sup.2) where v.sup.1=v.sub.1.sup.1, . . . , v.sub.n.sup.1 and v.sup.2=v.sub.1.sup.2, . . . , v.sub.n.sup.2 is equal to the number of bits in which v.sup.1 and v.sup.2 differ, such that it holds true that

(27) $d (v^{1}, v^{2}) = {.Math.}_{i = 1}^{n} v_{i}^{1} v_{i}^{2},$
wherein is a component-by-component exclusive-OR logic function.

(28) A code distance d.sub.min of a code is equal to the minimum Hamming distance between two different code words of the code C. If the code C is a linear code, then it holds true that
d.sub.min=min(d(v.sup.i,v.sup.j);v.sup.i,v.sup.jC;v.sup.iv.sup.j)
d.sub.min=min(w(v.sup.k,v.sup.kC)),
wherein

(29) $w (v) = {.Math.}_{j = 1}^{n} v_{j}$
denotes the Hamming weight of v, that is to say the number of ones of v.

(30) If the code C is a t-bit error correcting code having the minimum code distance d.sub.min, then t is determined in accordance with
2t+1d.sub.min2t+2

(31) In this regard, for example, a code having the minimum code distance d.sub.min=3 is a 1-bit error correcting code since
2.Math.1+1=332.Math.1+2=4
holds true.

(32) Known codes include linear codes and nonlinear codes. The Berger code (see e.g.

(33) http://en.wikipedia.org/wiki/Berger_code) shall be mentioned here as an example of a nonlinear code.

(34) From k information bits u.sub.1, . . . , u.sub.k, in the Berger code the associated check bits c.sub.1, . . . , c.sub.m result as

(35) $c_{1}, .Math., c_{m} = {({.Math.}_{i = 1}^{k} {\overline{u}}_{i})}_{bin},$

(36) such that the binary representation of the sum of the number of values 0 of the information bits determines the check bits. The Berger code detects all unidirectional errors, i.e. errors which only corrupt zeros into ones or only correct ones into zeros.

Exemplary Embodiment: (3,2,2) WOM Code

(37) Consideration is given to the case in which 3 blocks each composed of 2 useful data bits are stored as 3 blocks each composed of 3 useful data wits in a memory having the word width 19 at an address a=a.sub.1, . . . , a.sub.5 having the word width 5. These 3 blocks of useful data bits form the first 6 useful data bits and the 3 blocks of useful data wits assigned to them form the first 9 useful data wits.

(38) The useful data bits x.sub.1,x.sub.2 form the first block of the first useful data bits and are transformed into the first block of useful data wits y.sub.1,y.sub.2,y.sub.3 using the WOM code described in the table.

(39) Said WOM code is an (N.sub.W,n.sub.W,t)=(3,2,2) WOM code. As already explained above, in this case

(40) N.sub.W denotes the number of (useful data) wits (that is to say of transformed bits),

(41) n.sub.W denotes the number of bits (also referred to as data bits or useful data bits), and

(42) t denotes the number of write operations in which n.sub.W bits coded as N.sub.W wits can be written to the memory at an address a, without the memory having to be erased in the meantime.

(43) The useful data bits x.sub.3,x.sub.4 form the second block of the first useful data bits and are transformed into the second block of useful data wits y.sub.4,y.sub.5,y.sub.6 using the WOM code described in the table. Correspondingly, the useful data bits x.sub.5,x.sub.6 form the third block of the first useful data bits and are transformed into the third block of useful data wits y.sub.7,y.sub.8,y.sub.9 using the WOM code described in the table.

(44) As an example, the bit sequence
x.sub.1, . . . ,x.sub.6=10 00 11
is considered as first useful data bits.

(45) FIG. 1a illustrates a memory area 101 in which three blocks [y.sub.1,y.sub.2,y.sub.3], [y.sub.4,y.sub.5,y.sub.6] and [y.sub.7,y.sub.8,y.sub.9] of first useful data wits into which three blocks [x.sub.1,x.sub.2], [x.sub.3,x.sub.4] and [x.sub.5,x.sub.6] of first useful data bits are coded using the WOM code in accordance with the table above are intended to be stored at an address a.sub.1, . . . , a.sub.5. Said address reads for example: a.sub.1, . . . , a.sub.5=10011.

(46) The memory area 101 has a word width of 19 bits. Memory cells of the memory area 101 are designated by Z.sup.1,Z.sup.2, . . . , Z.sup.19 in FIG. 1a. The 19 bits are subdivided into 9 first (useful data) wits 102, five first check bits 103 and five second check bits 104.

(47) The memory cells Z.sup.1, . . . , Z.sup.9 serve for storing the data wits; the memory cells Z.sup.10, . . . , Z.sup.19 serve for storing check bits.

(48) By way of example, consideration is given to the case in which the memory area 101 is erased completely (and in an error-free manner) prior to writing. The memory cells Z.sup.i, i=1, . . . , 19 are thus in a state z.sub.i=0 before they are written to.

(49) In accordance with the bit sequence of useful data bits indicated by way of example above, the following relationships result for the blocks of in each case two useful data bits
x.sub.1,x.sub.2=10,
x.sub.3,x.sub.4=00,
x.sub.5,x.sub.6=11,

(50) These blocks of useful data bits are coded into useful data wits in accordance with the table as follows:
y.sub.1,y.sub.2,y.sub.3=.sup.1(x.sub.1,x.sub.2)=.sup.1(1,0)=100,
y.sub.4,y.sub.5,y.sub.6=.sup.1(x.sub.3,x.sub.4)=.sup.1(0,0)=000,
y.sub.7,y.sub.8,y.sub.9=.sup.1(x.sub.5,x.sub.6)=.sup.1(1,1)=010,

(51) In the exemplary embodiment under consideration, check bits are intended to be formed using a (14,9) code C, wherein the code C is a shortened Hamming code having an H-matrix

(52) $\begin{matrix} H = (\begin{matrix} 1 & 0 & 0 & 0 & 0 & 1 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 0 \\ 0 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & 0 \\ 0 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 0 & 0 & 1 & 1 \\ 0 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 0 & 1 & 0 \\ 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 0 & 1 \end{matrix}) = (I_{5}, P_{5, 9}^{T}) & (6) \end{matrix}$
and a G-matrix

(53) $\begin{matrix} G = (\begin{matrix} 1 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 1 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 1 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 \\ 1 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 \\ 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 \\ 0 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\ 0 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 \\ 0 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 \\ 0 & 0 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 \end{matrix}) = (P_{9, 5}, I_{9}) & (7) \end{matrix}$
wherein

(54) $\begin{matrix} P_{9, 5} = (\begin{matrix} 1 & 1 & 0 & 0 & 0 \\ 1 & 0 & 1 & 0 & 0 \\ 1 & 0 & 0 & 1 & 0 \\ 1 & 0 & 1 & 0 & 1 \\ 0 & 1 & 1 & 0 & 0 \\ 0 & 1 & 0 & 1 & 0 \\ 0 & 1 & 0 & 0 & 1 \\ 0 & 0 & 1 & 1 & 0 \\ 0 & 0 & 1 & 0 & 1 \end{matrix}), & (8) \end{matrix}$
holds true and

(55) 0 $\begin{matrix} P_{5, 9}^{T} = (\begin{matrix} 1 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 0 \\ 1 & 0 & 0 & 0 & 1 & 1 & 1 & 0 & 0 \\ 0 & 1 & 0 & 0 & 1 & 0 & 0 & 1 & 1 \\ 0 & 0 & 1 & 0 & 0 & 1 & 0 & 1 & 0 \\ 0 & 0 & 0 & 1 & 0 & 0 & 1 & 0 & 1 \end{matrix}) & (9) \end{matrix}$
is the transposed matrix of the matrix P.sub.9,5.

(56) In the present example, the five first check bits c.sub.1.sup.1,c.sub.2.sup.1,c.sub.3.sup.1,c.sub.4.sup.1,c.sub.5.sup.1 are determined in accordance with the relationship

(57) $\begin{matrix} \begin{matrix} c_{1}^{1}, c_{2}^{1}, c_{3}^{1}, c_{4}^{1}, c_{5}^{1} = f^{1} (x_{1}, x_{2}) f^{2} (x_{3}, x_{4}) f^{1} (x_{5}, x_{6}) .Math. P_{9, 5} = \\ = f^{1} (10) f^{1} (00) f^{1} (11) .Math. P_{9, 5} = \\ = 100000010 .Math. P_{9, 5} = \\ = 100000010 .Math. (\begin{matrix} 1 & 1 & 0 & 0 & 0 \\ 1 & 0 & 1 & 0 & 0 \\ 1 & 0 & 0 & 1 & 0 \\ 1 & 0 & 1 & 0 & 1 \\ 0 & 1 & 1 & 0 & 0 \\ 0 & 1 & 0 & 1 & 0 \\ 0 & 1 & 0 & 0 & 1 \\ 0 & 0 & 1 & 1 & 0 \\ 0 & 0 & 1 & 0 & 1 \end{matrix}) = 11110 \end{matrix} & (10) \end{matrix}$

(58) In a first write operation, therefore, at the address a.sub.1, . . . , a.sub.5=10011 the first data wits 100000010 are written to the memory cells Z.sup.1, . . . , Z.sup.9 and the first check bits 11110 are written to the memory cells Z.sup.10, . . . , Z.sup.14.

(59) FIG. 1b correspondingly shows the content or states of the memory area 101 having the address 10011 after the first write operation. In this case, the first check bits 11110 are formed from the first useful data wits and are not transformed into wits. The check bits are formed jointly for the first nine useful data wits (that is to say the three blocks of the first useful data wits). This has the advantage that fewer check bits are required compared with the case in which check bits would be formed for each individual block of wits.

(60) In a second write operation, the blocks of the second six useful data bits
x.sub.1,x.sub.2=11
x.sub.3,x.sub.4=10
x.sub.5,x.sub.6=11
are then intended to be coded as useful data wits and stored.

(61) The wits 100 are stored in the first three memory cells Z.sup.1,Z.sup.2,Z.sup.3 after the first write operation. The first block x.sub.1,x.sub.2=11 of the second useful data bits is coded into the second useful data wits
y.sub.1,y.sub.2,y.sub.3=.sup.2(x.sub.1,x.sub.2)=.sup.2(1,1)=101
and written to the memory cells Z.sup.1,Z.sup.2,Z.sup.3 which are occupied with 100 before the second writing process. The first useful data wits 100 are overwritten with the second useful data wits 101.

(62) The wits 000 are stored in the second three memory cells Z.sup.4,Z.sup.5,Z.sup.6 after the first write operation. The second block x.sub.3,x.sub.4=10 of the second useful data bits is coded into the second useful data wits
y.sub.4,y.sub.5,y.sub.6=.sup.1(x.sub.3,x.sub.4)=.sup.1(1,0)=100
and written to the memory cells Z.sup.4,Z.sup.5,Z.sup.6 which are occupied with 000 before the second writing process. The first useful data wits 000 are overwritten with the second useful data wits 100.

(63) The wits 010 are stored in the third three memory cells Z.sup.7,Z.sup.8,Z.sup.9 after the first write operation. The third block x.sub.5,x.sub.6=11 of the second useful data bits is coded into the second useful data wits
y.sub.7,y.sub.8,y.sub.9=.sup.1(x.sub.5,x.sub.6)=.sup.1(1,1)=010
and written to the memory cells Z.sup.7,Z.sup.8,Z.sup.9. The first useful data wits 010 are overwritten with the second useful data wits 010 having the same value.

(64) It should be noted here that overwriting of identical values can optionally also be omitted. In the example above, this means that if the first useful data wits 010 are overwritten by second useful data wits 010, the actual write operation can be omitted.

(65) To summarize, the following coding sequence accordingly arises in accordance with the present example here:

(66) TABLE-US-00002 second first bits Function first wits second bits Function wits x.sub.1 x.sub.2 = 10 f.sup.1 100 x.sub.1, x.sub.2 = 11 f.sup.2 101 x.sub.3 x.sub.4 = 00 f.sup.1 000 x.sub.3, x.sub.4 = 10 f.sup.1 100 x.sub.5 x.sub.6 = 11 f.sup.1 010 x.sub.5, x.sub.6 = 11 f.sup.1 010

(67) The five second check bits c.sub.1.sup.2, . . . , c.sub.5.sup.2 are formed in accordance with the relationship

(68) $\begin{matrix} \begin{matrix} c_{1}^{2}, c_{2}^{2}, c_{3}^{2}, c_{4}^{2}, c_{5}^{2} = f_{2} (x_{1}^{}, x_{2}^{}) f_{1} (x_{3}^{}, x_{4}^{}) f_{1} (x_{5}^{}, x_{6}^{}) .Math. P_{9, 5} = \\ = f_{2} (11) f_{1} (10) f_{1} (11) .Math. P_{9, 5} = \\ = (101100010) .Math. P_{9, 5} = \\ = (101100010) .Math. (\begin{matrix} 1 & 1 & 0 & 0 & 0 \\ 1 & 0 & 1 & 0 & 0 \\ 1 & 0 & 0 & 1 & 0 \\ 1 & 0 & 1 & 0 & 1 \\ 0 & 1 & 1 & 0 & 0 \\ 0 & 1 & 0 & 1 & 0 \\ 0 & 1 & 0 & 0 & 1 \\ 0 & 0 & 1 & 1 & 0 \\ 0 & 0 & 1 & 0 & 1 \end{matrix}) = 01001 \end{matrix} & (11) \end{matrix}$

(69) The second nine useful data wits 101 100 010 are written to the memory cells Z.sup.1, . . . ,Z.sup.9 in the second write operation. The memory cells have the states z.sub.1.sup.1, . . . , z.sub.9.sup.1=100 000 010 after the first write operation. The second write operation is applicable to these states because not a single state experiences a transition from 1 to 0.

(70) The second check bits c.sub.1.sup.2,c.sub.2.sup.2,c.sub.3.sup.2,c.sub.4.sup.2,c.sub.5.sup.2=01001 are written to the memory cells Z.sup.15, . . . , Z.sup.19 in the second write operation.

(71) FIG. 1c shows the content or states of the memory cells Z.sup.1, . . . , Z.sup.19 after the second write operation.

(72) After the first write operation, the first nine useful data wits 100 000 010 are stored in the memory cells Z.sup.1, . . . ,Z.sup.9 and the first check bits 11110 are stored in the memory cells Z.sup.10, . . . , Z.sup.14. This results in a code word of the code C under consideration (here: Hamming code):
11110 100 000 010.

(73) After the second write operation, the second nine useful data wits 101 100 010 are stored in the memory cells Z.sup.1, . . . , Z.sup.9 and the second check bits 01001 are stored in the memory cells Z.sup.15, . . . , Z.sup.19. This results in a code word of the code C under consideration:
01001 101 100 010.

(74) It is advantageous to store the first check bits 103 and the second check bits 104 without transforming them into wits. In this case, the combination of wits and check bits is not WOM-coded. In this respect, e.g. known error correcting codes can be applied to data wits. Moreover, a coding of the check bits into check wits using a WOM code can have the effect that as a result of errors in the stored check wits additional errors occur in the check bits which are required for correcting the data wits.

(75) If, for example, the bits 10 coded as wits .sup.1(1,0)=1,0,0 are written to a memory and if, for example, a 1-bit error occurs in the second position of the wits, such that 1,0,0 is corrupted to 1,1,0, then from the table it is evident that the wits 1,1,0 correspond to the bits 0,1:
WOM coding: x.sub.1,x.sub.2=10.fwdarw..sup.1(x.sub.1,x.sub.2)=100
1-bit error in wits: 100.fwdarw.110
WOM decoding: .sup.2(110)=0110

(76) Consequently, a very frequently occurring 1-bit error in the check bits coded as wits can lead to a 2-bit error in the inverse-transformed bits. If the check bits were also stored in a WOM-coded manner, errors in the check wits could correspondingly affect the number of errors in the check bits, which would increase the complexity of the error correction and require more complex codes.

(77) The number of check bits of a customary error correcting linear code having k information positions, for example of a Hamming code, of a Hsiao code or of a BCH code, increases proportionally to log.sub.2(k) wherein log.sub.2 describes the logarithm to the base two, such that the number of check bits is small in comparison with the information positions particularly for large values of k.

(78) Using WOM codes for transforming the relatively large number of useful data bits into useful data wits significantly reduces the number of required memory cells for storing the useful data. However, the relatively small number of memory cells for storing the check bits is doubled, for example. In the examples explained here, it is possible to use an error code C having a relatively small code distance which requires only a small number of check bits. That allows a fast error correction and requires a small chip area for realizing a decoding circuit and/or a coding circuit.

(79) In the present example, the first check bits are stored in the memory cells Z.sup.10, . . . , Z.sup.14 in the first write operation and the second check bits are stored in the second memory cells Z.sup.15, . . . , Z.sup.19 in the second write operation.

(80) When reading out the data from the memory area 102 it is known whether the memory was written to for the first time or for the second time or whether the check bits associated with the data wits read out are first check bits 103 or second check bits 104 (or it is known where the respective check bits are stored).

(81) By way of example, the first check bits can be stored in a memory area of first check bits in the first write operation. Correspondingly, the second check bits can be stored in a memory area of second check bits in the second write operation. The two memory areas for first and second check bits can be embodied for example differently from one another, that is to say e.g. physically separately from one another. During reading after the respective write operation, the respectively appropriate physical memory is then addressed for access to the respective check bits.

(82) Option: Data Wits and Associated Check Bits in Different Memory Areas

(83) It is also possible to write data wits and associated check bits to different memory areas and/or to different memories.

(84) If the data wits are stored for example in a first memory, in which a first binary value (for example 1) cannot be overwritten by a second binary value (for example 0) (without the corresponding memory area being erased beforehand), then the check bits can also be written to a second memory, in which the stored bits can be overwritten arbitrarily. As a result, the word width of the values to be stored becomes smaller since then only either the first check bits or the second check bits are stored.

(85) The memory for storing the data wits can be e.g. a flash memory; the memory for storing the check bits can be e.g. an SRAM. The SRAM can be loaded with the corresponding check bits e.g. upon initialization.

(86) Furthermore, it is an option to use some other non-volatile memory for the check bits, for example an MRAM or an RRAM. Moreover, if appropriate, a (non-volatile) memory area already present in the system can be used or concomitantly used for this purpose.

(87) Interpretation of the First Check Bits: Marker

(88) As a further exemplary embodiment, an explanation is given below of how, on the basis of the states of the first memory cells for storing the check bits it is possible to determine whether the check bits associated with the data wits read out were stored in the first memory cells for storing check bits or in the second memory cells for storing check bits.

(89) As shown by way of example above, the data wits formed from the blocks of the first data bits and the data wits formed from the blocks of the second data bits are written to the same memory cells at the address a.

(90) The first check bits c.sub.1.sup.1, . . . , c.sub.m.sup.1 of a code word of a code C.sup.1 are written as first check bits to first memory cells for storing the first check bits. If the second check bits c.sub.1.sup.2, . . . , c.sub.m.sup.2 of a code word of a code C.sup.2 are written as second check bits to second memory cells for storing the second check bits, which are different than the first memory cells for storing the first check bits, then the first memory cells for storing the first check bits can be overwritten with a marker (also referred to as a flag or a marking), for example with the marker

(91) $\underset{m}{\underset{}{1, .Math., 1}}$

(92) if the marker itself is not a permissible check bit combination of a code word of the code C.sup.1 used.

(93) Moreover, it is possible to write the second check bits to the first memory cells for storing check bits if that is possible in an error-free manner and without an additional erasure operation, even though these memory cells had already been written to previously in the first write operation.

(94) The second check bits can be written to the first memory cells for storing the check bits if none of those memory cells to which a check bit 0 (that is to say a state 0) is intended to be written in the second write operation is in a state 1 after the first write operation. In other words (without prior erasure, as already explained) a state change from 0 to 1 is possible, but not conversely from 1 to 0. Moreover, it is possible for a memory cell to remain in its state 0 or 1 without prior erasure.

(95) If no error occurs, the second check bits in the second write operation can in particular then be written to the same memory cells as the first check bits, provided that
m=m
holds true, that is to say that the same number of memory cells is intended to be used for the check bits, and provided that
c.sub.1.sup.2c.sub.1.sup.1, . . . ,c.sub.m.sup.2c.sub.m.sup.1
holds true.

(96) Otherwise the second check bits can be written to the second memory cells for storing check bits, wherein in this case the first memory cells for storing check bits optionally acquire the marking m.sub.1, . . . , m.sub.m, that is to say are correspondingly overwritten.

(97) Such a procedure can be advantageous in particular if for example at an address
a=a.sub.1,a.sub.2,a.sub.3,a.sub.4,a.sub.5
the wits
0, . . . ,0
are intended to be stored, which are assigned the check bits

(98) $\underset{m}{\underset{}{0, .Math., 0}}$
which can be overwritten by arbitrary values in an error-free manner.

(99) By way of example, the value
1, . . . ,1
can be chosen as a marker. This is possible provided that this marker itself does not represent a valid check bit combination of a code word. Other markers can optionally also be used provided that they do not contribute to a (valid) code word.

(100) When reading from the memory cells for storing the first check bits, these bits are used as first check bits if they are not identical to the marker. Otherwise, that is to say if the bits read in the memory cells for storing the first check bits are identical to the marker, then use is made of the memory cells for storing the second check bits as check bits.

(101) An error can thus be detected if the bits read out from the memory cells of the first check bits are identical to the marker and the bits read out from the memory cells of the second check bits as check bits together with the wits read out do not form a valid code word or if the bits read out from the memory cells of the first check bits are not identical to the marker and these bits as check bits together with the wits read out do not form a valid code word.

(102) Extension of the Code by c.sub.m+1

(103) A description is given below of an exemplary embodiment according to which, from a given code in which the bits 1, . . . , 1 are check bits of a code word, it is possible to determine a modified code in which the bits 1, . . . , 1 are not check bits of a valid code word.

(104) If the given code has m check bits c.sub.1, . . . ,c.sub.m, then it is possible to add a further check bit c.sub.m+1, such that c.sub.m+1 is an XOR logic function (XOR: exclusive-OR) of an even number of check bits of the given code.

(105) In this regard, it is possible, for example, to determine a further check bit c.sub.m+1 from the first two check bits c.sub.1 and c.sub.2 in accordance with
c.sub.m+1=c.sub.1c.sub.2
If c.sub.1=c.sub.2= . . . =C.sub.m=1 then c.sub.m+1=0 and

(106) $c_{1}, .Math., c_{m + 1} = \underset{m + 1}{\underset{}{1, .Math., 1}}$
are not check bits of a code word of the modified code.

(107) Correspondingly, m=m+1 memory cells can be provided for storing m+1 first check bits and just m memory cells can be provided for storing m second check bits. It is then not necessary for the (m+1)-th check bit derived from the first m check bits to be stored during the write operation in the memory cells for storing the second check bits since the marker is entered only into the first m memory cells for storing the check bits.

(108) It is also possible to add a plurality of additional check bits in order to derive from a given code a modified code containing a bit sequence 1, . . . , 1 which are not check bits of a valid code word.

(109) By way of example, let there be a code C.sup.2 having 6 data bits and 6 check bits with the H-matrix

(110) $\begin{matrix} H^{2} = (\begin{matrix} 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 1 & 0 & 1 & 0 \\ 0 & 1 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 0 & 1 \\ 0 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 1 & 0 & 0 & 1 \\ 0 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 1 \\ 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 0 & 1 & 1 & 0 \\ 0 & 0 & 0 & 0 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 1 \end{matrix}) = (I_{6}, P_{6, 6}^{T}) & (12) \end{matrix}$
and the G-matrix

(111) $\begin{matrix} G^{1} = (\begin{matrix} 1 & 1 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 \\ 1 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\ 0 & 1 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 1 & 0 & 0 \\ 1 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 \\ 0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 \end{matrix}) = (P_{6, 6}, I_{6}) & (13) \end{matrix}$
where

(112) $\begin{matrix} P_{6, 6} = (\begin{matrix} 1 & 1 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 1 & 1 \\ 1 & 0 & 1 & 1 & 0 & 0 \\ 0 & 1 & 0 & 0 & 1 & 1 \\ 1 & 0 & 0 & 1 & 1 & 0 \\ 0 & 1 & 1 & 0 & 0 & 1 \end{matrix}) & (14) \end{matrix}$
and

(113) $\begin{matrix} P_{6, 6}^{T} = (\begin{matrix} 1 & 0 & 1 & 0 & 1 & 0 \\ 1 & 0 & 0 & 1 & 0 & 1 \\ 1 & 0 & 1 & 0 & 0 & 1 \\ 0 & 1 & 1 & 0 & 0 & 1 \\ 0 & 1 & 0 & 1 & 1 & 0 \\ 0 & 1 & 0 & 1 & 0 & 1 \end{matrix}) & (15) \end{matrix}$

(114) The vector
c.sub.1, . . . ,c.sub.6,u.sub.1, . . . ,u.sub.6=1, . . . ,1=All1
is a code vector since each row of the H-matrix contains an even number of ones and
c.sub.1, . . . ,c.sub.6=1, . . . ,1
is a partial word of a code word. In this case, All1 denotes a vector of all ones (composed of 12 ones in the present case).

(115) A code C.sup.1 is derived from the code C.sup.2 by an additional check bit
c.sub.7=c.sub.1c.sub.3=u.sub.5u.sub.6
being added, such that

(116) 0 $c_{1}, .Math., c_{7} = \underset{7}{\underset{}{1, .Math., 1}}$
is not a partial word of a code word.

(117) For the G-matrix G.sup.1 of the code C.sup.1 it holds true that

(118) $\begin{matrix} G^{1} = (\begin{matrix} 1 & 1 & 1 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 \\ 1 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\ 0 & 1 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 1 & 0 & 0 \\ 1 & 0 & 0 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 1 & 0 \\ 0 & 1 & 1 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 1 \end{matrix}) = (P_{6, 7}, I_{6}), & (16) \end{matrix}$
where

(119) $\begin{matrix} P_{6, 7} = (\begin{matrix} 1 & 1 & 1 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 1 & 1 & 0 \\ 1 & 0 & 1 & 1 & 0 & 0 & 0 \\ 0 & 1 & 0 & 0 & 1 & 1 & 0 \\ 1 & 0 & 0 & 1 & 1 & 0 & 1 \\ 0 & 1 & 1 & 0 & 0 & 1 & 1 \end{matrix}) . & (17) \end{matrix}$
If c.sub.1=c.sub.3=1 holds true, then
c.sub.7=c.sub.1c.sub.3=u.sub.5u.sub.6=0
and

(120) $\underset{7}{\underset{}{1, .Math., 1}}$
are not check bits of a valid code word of the code C.sup.1.

(121) FIG. 2 shows six memory cells 201 Z.sup.1, . . . ,Z.sup.6, seven memory cells 202 Z.sup.7, . . . ,Z.sup.13 and six memory cells 203 Z.sup.14, . . . , Z.sup.19. Binary values can be stored in these 19 memory cells 201 to 203 at an address 204 a=a.sub.1,a.sub.2,a.sub.3, which is given here by 101 by way of example.

(122) From two blocks [x.sub.1,x.sub.2], [x.sub.3,x.sub.4] of first data bits, in the first writing process in accordance with the WOM code (see table above) taking account of the states z.sup.1,z.sup.2,z.sup.3, and z.sup.5,z.sup.6,z.sup.7 of the memory cells Z.sup.1,Z.sup.2,Z.sup.3 and Z.sup.4,Z.sup.5,Z.sup.6, the two blocks of first data wits [y.sub.1,y.sub.2,y.sub.3] and [y.sub.5,y.sub.6,y.sub.7] are determined. If the memory cells 201 are erased completely and in an error-free manner and are in each case in the state 0, then it holds true that
[y.sub.1,y.sub.2,y.sub.3]=.sup.1([x.sub.1,x.sub.2])
and
[y.sub.4,y.sub.5,y.sub.6]=.sup.1([x.sub.3,x.sub.4]).

(123) The first data wits y.sub.1,y.sub.2,y.sub.3,y.sub.5,y.sub.6 are written to the memory cells 201 having the states z.sub.1.sup.1, . . . , z.sub.6.sup.1 after the write operation. In the first write operation, first check bits c.sub.1.sup.1, . . . , c.sub.7.sup.1 are determined in accordance with the code C.sup.1 according to the relationship
c.sub.1.sup.1, . . . ,c.sub.7.sup.1=(.sup.1([x.sub.1,x.sub.2]),.sup.1([x.sub.3,x.sub.4])).Math.P.sub.6,7(18)
and are written to the memory cells 202.

(124) Since for the first check bits

(125) $c_{1}^{1}, .Math., c_{7}^{1} \underset{7}{\underset{}{1, .Math., 1}}$
holds true, the memory cells 202 are not occupied with seven successive binary 1-values 1111111 after the first writing process.

(126) In the second write operation it is possible to determine from the two blocks [x.sub.1,x.sub.2][x.sub.3,x.sub.4] of second data bits to be written and depending on the states z.sub.1.sup.1, . . . , z.sub.6.sup.1 of the memory cells Z.sup.1, . . . ,Z.sup.6 the blocks of the second data wits in accordance with
[y.sub.1,y.sub.2,y.sub.3]=.sup.i.sup.2([x.sub.1,x.sub.2])
and
[y.sub.4,y.sub.5,y.sub.6]=.sup.i.sup.2([x.sub.3,x.sub.4])

(127) In this case, .sup.i.sup.2 denotes the transformation of the bits into wits which is to be used in the second write operation, and which depends on the value of the data wits written in the first write operation in the memory cells 201.

(128) The second check bits c.sub.1.sup.2, . . . , c.sub.6.sup.2 are formed in accordance with the code C.sup.2 according to the relationship
c.sub.1.sup.2, . . . ,c.sub.6.sup.2=(.sup.i.sup.2([x.sub.1,x.sub.2]),.sup.i.sup.2([x.sub.3,x.sub.4])).Math.P.sub.6,6(19)
and are written to the memory cells 203. The value

(129) $\underset{7}{\underset{}{1, .Math., 1}}$
is then written to the memory cells 202.

(130) In the first write operation the first seven check bits c.sub.1.sup.1, . . . , c.sub.7.sup.1 are formed in accordance with the code C.sup.1. In the second write operation the second six check bits are determined in accordance with the code C.sup.2. By way of example, C.sup.1 and C.sup.2 are different codes.

(131) It thus follows that:

(132) if the value 1111111 is already stored in the memory cells 202, the check bits corresponding to the stored data wits are situated in the memory cells 203, that is to say the memory cells for storing the second check bits.

(133) By contrast, if the value stored in the memory cells 202 for storing the first check bits is not equal to 1111111, the check bits corresponding to the stored data wits can be found in the memory cells 202 for storing the first check bits.

(134) FIG. 2 shows the corresponding memory cells 201, 202 and 203 at the address 204 of the memory. The address 204 has the value 101, for example. 19 bits are stored at this address: 6 data wits, 7 first check bits and 6 second check bits. In the first write operation, the first check bits are stored in 7 memory cells 202 in accordance with the code C.sup.1. In the second write operation, the second check bits are stored in 6 memory cells 203 in accordance with the code C.sup.2, wherein the 7 first check bits of the memory cells 202 in this case are overwritten with the value 1111111. This value 1111111 is also referred to as a marking. The marking thus makes it possible to determine whether the critical check bits are the first check bits or the second check bits or whether the precisely relevant check bits can be found in the memory area 202 or in the memory area 203.

Example: Memory Cells are Partly in the State 1

(135) By way of example, an explanation is given of a case in which a portion of the memory cells are in the state 1 before said memory cells are written to. Such a case can occur, for example, if not all the memory cells were successfully erased in a previous erasure operation on account of an aging memory.

(136) By way of example, a block of two data bits [x.sub.1.sup.1,x.sub.2.sup.1] is intended to be transformed into a block of three data wits [y.sub.1,y.sub.2,y.sub.3] using the WOM code in accordance with the table above, in order to write the data wits to memory cells Z.sup.1,Z.sup.2,Z.sup.3 having the states z.sub.1,z.sub.2,z.sub.3.

(137) It is possible to write the wits .sup.1([x.sub.1.sup.1,x.sub.2.sup.1])=y.sub.1.sup.1,y.sub.2.sup.1,y.sub.3.sup.1 to the memory cells Z.sup.1,Z.sup.2,Z.sup.3 in an error-free manner if it holds true that:
y.sub.1.sup.1z.sub.1,y.sub.2.sup.1z.sub.2,y.sub.3.sup.1z.sub.3 or z.sub.1y.sub.1.sup.1 custom character z.sub.2y.sub.2.sup.1z.sub.2y.sub.3.sup.1=0 (20)

(138) Furthermore, it is possible to write the wits .sup.2([x.sub.1.sup.1,x.sub.2.sup.1])=y.sub.1.sup.2,y.sub.2.sup.2,y.sub.3.sup.2 to the memory cells Z.sup.1,Z.sup.2,Z.sup.3 in an error-free manner if it holds true that:
y.sub.1.sup.2z.sub.1,y.sub.2.sup.2z.sub.2,y.sub.3.sup.2z.sub.3 or z.sub.1y.sub.1.sup.2 custom character z.sub.2y.sub.2.sup.2z.sub.2y.sub.3.sup.2=0 (21)

(139) If z.sub.1,z.sub.2,z.sub.3=0,0,0, for any occupancy of [x.sub.1.sup.1,x.sub.2.sup.1] it is possible to write both .sup.1([x.sub.1.sup.1,x.sub.2.sup.1])=y.sub.1.sup.1,y.sub.2.sup.1,y.sub.3.sup.1 and .sup.2([x.sub.1.sup.1,x.sub.2.sup.1])=y.sub.1.sup.2,y.sub.2.sup.2,y.sub.3.sup.2 as a block of 3 wits to the memory cells.

(140) For specific values z.sub.1,z.sub.2,z.sub.3 it is possible to write a block [x.sub.1.sup.1,x.sub.2.sup.1] of 2 data bits as a block of 3 data wits .sup.i([x.sub.1.sup.1,x.sub.2.sup.1])=y.sub.1.sup.i,y.sub.2.sup.i,y.sub.3.sup.i where i{1,2} in an error-free manner to memory cells Z.sup.1,Z.sup.2,Z.sup.3 which are in the state z.sub.1,z.sub.2,z.sub.3 if there is an i where i{1,2}, such that it holds true that:
z.sub.1y.sub.1.sup.i custom character z.sub.2y.sub.2.sup.iz.sub.3y.sub.3.sup.i=0(22)

(141) If only one individual state of the three states z.sub.1,z.sub.2,z.sub.3 assumes the value 1, then it is possible to write any occupancy of two bits [x.sub.1.sup.1,x.sub.2.sup.1] coded as 3 wits to the corresponding memory cells in an error-free manner since for .sup.1([x.sub.1.sup.1,x.sub.2.sup.1])=y.sub.1.sup.1,y.sub.2.sup.1,y.sub.3.sup.1 and .sup.2([x.sub.1.sup.1,x.sub.2.sup.1])=y.sub.1.sup.2,y.sub.2.sup.2,y.sub.3.sup.2 according to the WOM code table above it holds true that:
y.sub.1.sup.1=y.sub.1.sup.2,
y.sub.2.sup.1=y.sub.2.sup.2,
y.sub.3.sup.1=y.sub.3.sup.2.

(142) If only one of the states z.sub.1,z.sub.2,z.sub.3, e.g. z.sub.1, is equal to 1, then either z.sub.1y.sub.1.sup.1=0 or z.sub.1y.sub.1.sup.2=0.

(143) It is also possible for states z.sub.1.sup.C.sup.1, . . . , z.sub.m+1.sup.C.sup.1 or states z.sub.1.sup.C.sup.2, . . . , z.sub.m.sup.C.sup.2 of memory cells Z.sup.1,C.sup.1, . . . , Z.sup.m+1,C.sup.1 or Z.sup.1,C.sup.2, . . . , Z.sup.m,C.sup.2 for storing check bits to be equal to 1 before the check bits are written to these memory cells.

(144) In this regard, it is possible for the check bits c.sub.1, . . . c.sub.m+1 to be written to the memory cells Z.sup.1,C.sup.1, . . . , Z.sup.m+1,C.sup.1 in an error-free manner if it holds true that:
z.sub.1.sup.C.sup.1c.sub.1 custom character z.sub.2.sup.C.sup.1c.sub.2. . . ,z.sub.m+1.sup.C.sup.1c.sub.m+1=0(23)

(145) It is correspondingly possible to write the check bits c.sub.1, . . . , c.sub.m to the memory cells Z.sup.1,C.sup.2, . . . , Z.sup.m,C.sup.2 having the states z.sub.1.sup.C.sup.2, . . . , z.sub.m.sup.C.sup.2 if it holds true that:
z.sub.1.sup.C.sup.2c.sub.1 custom character z.sub.2.sup.C.sup.2c.sub.2 . . . z.sub.m.sup.C.sup.2c.sub.m=0(24)

(146) In this case, C.sup.1 denotes the first code and C.sup.2 denotes the second code.

(147) If it is possible to write the first check bits c.sub.1, . . . , c.sub.m+1 to the memory cells 202 Z.sup.1,C.sup.1, . . . , Z.sup.m+1,C.sup.1 in an error-free manner, then said check bits are actually stored in said memory cells 202. By contrast, if it is not possible to write the first check bits to the memory cells 202 Z.sup.1,C.sup.1, . . . , Z.sup.m+1,C.sup.1 in an error-free manner, then said first check bitsif that is possibleare written to the memory cells 203 Z.sup.1,C.sup.2, . . . , Z.sup.m,C.sup.2.

(148) Optionally, in this case, the marking, that is to say the value 1111111, can be written to the memory cells 202. It should be assumed here that the marking is not a valid code word of the first code C.sup.1, that is to say that the following holds true:

(149) $c_{1}, .Math., c_{m + 1} \underset{m + 1}{\underset{}{1, .Math., 1}}$

(150) If it is not possible to write the data bits coded as wits to the corresponding memory cells in an error-free manner or to write the check bits to the provided memory cells in an error-free manner, then it is an option to erase the memory area and then to write to it again, or else a different memory area can be used. This can be advantageous particularly if the original memory area has a defect.

(151) A further option comprises determining a number of the memory cells possibly written to erroneously per memory area, and comparing this number with a predefined threshold value. In the event of the threshold value being reached and/or exceeded, the memory area can be erased in order then to be written to again. Alternatively, a different memory area can be used instead of this memory area.

(152) It is also possible to determine a number d.sub.D of the memory cells to which data wits were written erroneously and to determine a number d.sub.P of the memory cells to which check bits were written erroneously and, depending on the values d.sub.D and d.sub.P, to erase a specific memory area, or to use a different memory area.

(153) The number of memory cells written to erroneously can be determined for example by a comparison of the data to be written with the data read out after the writing process.

(154) A memory cell is in an erroneous state if it is in the state 1 before the writing process and a value 0 is written to this memory cell, wherein the state of the cell does not change, such that it erroneously has the value 1 after writing.

(155) It is possible to erase a memory area if a state of a memory cell of this memory area is erroneous after writing.

(156) It is also possible, for example, using an error correcting and/or error detecting code, to erase a memory area if a number of bit errors which are not correctable by the code are present. It is furthermore an option already to erase the memory area if a specific number of bit errors are present, even if this number would still be correctable by the code.

Example: Storing Useful Data Wits when Bit Errors Occur

(157) A description will be given below of an example according to which k blocks x.sup.1,x.sup.2, . . . ,x.sup.k of useful data bits which are coded as k blocks y.sup.1,y.sup.2, . . . ,y.sup.k of useful data wits are stored in a memory at an address a if at least one error occurs.

(158) x.sup.i denotes the useful data bits of the i-th block of useful data bits and y.sup.i denotes the useful data wits of the i-th block [y.sup.i] of useful data wits where i=1, . . . , k.

(159) By way of example, the following steps can be carried out:

(160) 1. Coding the bits of the blocks of useful data bits x.sup.i into wits of the blocks of useful data wits to form overall a number of N useful data wits in accordance with a WOM code according to the relationship
y.sup.1=.sup.i.sup.1(x.sup.1), . . . ,y.sup.k=.sup.i.sup.k(x.sup.k),

(161) wherein for j=1, . . . ,k the coding functions .sup.i.sup.j of the WOM code used, depending on the states of the memory cells to which the wits of the block y.sup.j are written and depending on x.sup.j, are selected from the possible coding functions of the WOM code such that a number Anz1.sup.j of the states of said memory cells which are equal to 1 and to which a with having the value 0 is written is minimal.

(162) 2. Determining m check bits c=c.sub.1, . . . , c.sub.m, such that
.sup.i.sup.1(x.sup.1), . . . ,.sup.i.sup.k(x.sup.k),c

(163) bits of a code word of an error detecting and/or error correcting code C at least of the length N+m+1 result, wherein m1 holds true.

(164) 3. If the number of states of the memory cells which are equal to 1 and to which the value 0 is intended to be written reaches or exceeds a predefined threshold value S.sub.1 where S.sub.10, i.e. if the condition

(165) ${.Math.}_{j = 1}^{k} Anz 1^{j} S_{1}$

(166) is fulfilled, the memory area addressed by the address a is erased.

(167) 4. Determining a number Anz2.sup.c of first memory cells for storing check bits which are in the state 1 and to which a check bit of the check bits c which has the value 0 is intended to be written at the address a.

(168) 5. If the number Anz2.sup.c reaches or exceeds a threshold value S.sub.2 where S.sub.20, that is to say if the following condition
Anz2.sup.cS.sub.2,

(169) is fulfilled, a number Anz3.sup.c of second memory cells for storing check bits which are in the state 1 and to which a check bit of the check bits c having the value 0 is intended to be written to the address a is determined.

(170) If the number Anz3.sup.cS.sub.3, then the check bits c are written to the memory cells 203 of the second check bits, wherein S.sub.30 is a predefined threshold value.

(171) If the number Anz3.sup.c>S.sub.3, the memory area containing the address a is erased, wherein S.sub.30 is a predefined threshold value.

(172) 6. If the condition

(173) ${.Math.}_{j = 1}^{k} Anz 1^{j} + Anz 2^{c} S_{4}$

(174) and/or the condition

(175) ${.Math.}_{j = 1}^{k} Anz 1^{j} + Anz 3^{c} S_{4},$

(176) are/is fulfilled, wherein S.sub.40 is a predefined threshold value, then the memory area containing the address a is erased.

(177) The above steps thus check whether, for the useful data wits and/or the (first and/or second) check bits, there is (in each case) a number of memory cells which already have the state 1, to which the value 0 is intended to be written and which therefore can no longer be transformed to the state 0 without prior erasure. If this is the case and if the respective number or a combination of numbers exceeds a (at least one) threshold value, then the memory area is erased. It is advantageous here that the useful data wits in combination with the check bits can represent a code word of an error detecting and/or error correcting code, such that a specific set of erroneous bits (that is to say those bits which have the value 1 instead of the value 0) can be corrected.

(178) If a t-bit error correcting code is used for example for determining the first check bits c.sup.1 from the k blocks of the first data wits and for determining the second check bits c.sup.2 from the blocks of the second data wits, then it is possible to correct all erroneous values of the memory cells which arise upon writing values 0 in memory cells which are in the state 1, if S.sub.4t holds true and if no further errors occur in the memory.

(179) If S.sub.4+t holds true, then even further memory errors can be corrected in addition to the erroneous values that occur upon writing a value 0 to those memory cells which are in the state 1.

Example: Detection of Address Errors

(180) An exemplary embodiment is specified below according to which errors in the addresses can be detected.

(181) The address bits can in this case be interpreted as additional bits. Such additional bits are, in particular, bits which are used in addition to the data wits for forming the check bits. Furthermore, it is an option to provide at least one inversion bit which is added to the data bits in order to describe whether and which data bits (or groups of data bits) were inverted. Additional bits can also comprise at least one indicator bit (password).

(182) By way of example, a code C shall be specified having the code distance 3, the H-matrix

(183) 0 $\begin{matrix} H = (\begin{matrix} 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 1 & 0 \\ 0 & 1 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 0 & 1 & 0 & 1 & 1 & 0 \\ 0 & 0 & 1 & 0 & 0 & 0 & 1 & 0 & 1 & 0 & 0 & 1 & 0 & 1 & 0 & 1 \\ 0 & 0 & 0 & 1 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 1 & 0 & 1 & 0 & 1 \\ 0 & 0 & 0 & 0 & 1 & 0 & 0 & 1 & 0 & 1 & 1 & 0 & 1 & 0 & 0 & 1 \\ 0 & 0 & 0 & 0 & 0 & 1 & 0 & 1 & 0 & 1 & 0 & 1 & 1 & 0 & 1 & 0 \end{matrix}) = (I_{6}, P_{6, 10}^{T}) & (25) \end{matrix}$
and the G-matrix

(184) $\begin{matrix} G = (\begin{matrix} 1 & 1 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 1 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 1 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 \\ 1 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 \\ 0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 \\ 1 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\ 0 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 \\ 1 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 \\ 0 & 0 & 1 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 \end{matrix}) = (P_{10, 6}, I_{10}) & (26) \end{matrix}$
where

(185) $\begin{matrix} P_{10, 6} = (\begin{matrix} 1 & 1 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 1 & 1 \\ 1 & 0 & 1 & 1 & 0 & 0 \\ 0 & 1 & 0 & 0 & 1 & 1 \\ 1 & 0 & 0 & 1 & 1 & 0 \\ 0 & 1 & 1 & 0 & 0 & 1 \\ 1 & 0 & 0 & 0 & 1 & 1 \\ 0 & 1 & 1 & 1 & 0 & 0 \\ 1 & 1 & 0 & 0 & 0 & 1 \\ 0 & 0 & 1 & 1 & 1 & 0 \end{matrix}) . & (27) \end{matrix}$

(186) All columns of the H-matrix have an odd number of ones, such that the code is a shortened Hsiao code. This shortened Hsiao code allows the correction of 1-bit errors and the detection of 2-bit errors.

(187) By way of example, two blocks of data bits [x.sub.1,x.sub.2] and [x.sub.3,x.sub.4] are coded into two blocks of data wits [y.sub.1,y.sub.2,y.sub.3] and [y.sub.4,y.sub.5,y.sub.6] in accordance with the WOM code discussed here (see table above).

(188) FIG. 3 symbolically shows a memory area comprising an address a, wherein 18 bits can be stored at each address a. These 18 bits correspond to 18 memory cells Z.sup.1, . . . ,Z.sup.18 and are subdivided into memory cells 301 for data wits (memory cells Z.sup.1, . . . ,Z.sup.6), memory cells 302 for first check bits c.sup.1=c.sub.1.sup.1, . . . , c.sub.6.sup.1 (memory cells Z.sup.7, . . . , Z.sup.12), and memory cells 303 for second check bits c.sup.2=c.sub.1.sup.2, . . . , c.sub.6.sup.2 (memory cells Z.sup.13, . . . , Z.sup.18).

(189) The address a is subdivided into 4 bits, such that it holds true that: a=a.sub.1,a.sub.2,a.sub.3,a.sub.4.

(190) The memory cells 301 serve for storing the data wits y.sub.1, . . . , y.sub.6 of the blocks [y.sub.1,y.sub.2,y.sub.3], [y.sub.4,y.sub.5,y.sub.6] of the data wits.

(191) The check bits c.sup.1=c.sub.1.sup.1, . . . , c.sub.6.sup.1 are determined with inclusion of the address a=a.sub.1, . . . , a.sub.4 such that it holds true that
c.sup.1=c.sub.1.sup.1, . . . ,c.sub.6.sup.1=(.sup.i.sup.1,1([x.sub.1,x.sub.2]),.sup.i.sup.1,2([x.sub.3,x.sub.4]),a.sub.1, . . . ,a.sub.4).Math.P.sub.10,6,(28)
wherein the functions .sup.i.sup.1,1, .sup.i.sup.1,2 are the functions which transform the bits x.sub.1, . . . , x.sub.4 of the blocks [x.sub.1,x.sub.2],[x.sub.3,x.sub.4] into the corresponding blocks of data wits in accordance with the WOM code according to the table indicated above, depending on the occupancy of the memory cells 301. If for example all the memory cells Z.sup.1, . . . ,Z.sup.6 are in the state 0 before the first write operation, it holds true that .sup.i.sup.1,1=.sup.i.sup.1,2=.sup.1.

(192) In the example described here, in the first write operation the intention is to store the blocks [x.sub.1,x.sub.2]=[1,0] and [x.sub.3,x.sub.4]=[1,1] at the address 1010 and the blocks [x.sub.1,x.sub.2]=[0,1] and [x.sub.3,x.sub.4]=[0,1] at the address 1011 coded as data wits. It is assumed that all the memory cells 301 have the value 0 before the first write operation.

(193) The block of the data bits [x.sub.1,x.sub.2]=[1,0] is transformed into the block of the data wits
[y.sub.1,y.sub.2,y.sub.3]=.sup.1([1,0])=[1,0,0]
and the block of the data bits [x.sub.3,x.sub.4]=[1,1] is transformed into the block of the data wits
[y.sub.4,y.sub.5,y.sub.6]=.sup.1([1,1])=[0,1,0]

(194) Since the data wits y.sub.1, . . . , y.sub.6=100 010 are intended to be stored at the address 1010, the check bits c.sup.1=c.sub.1.sup.1, . . . , c.sub.6.sup.1 result as
c.sub.1.sup.1, . . . ,c.sub.6.sup.1=(100 010 1010).Math.P.sub.10,6=001 100.

(195) The data wits y.sub.1, . . . , y.sub.6=100 010 are stored in the memory cells 301 at the address 1010. The check bits c.sub.1.sup.1, . . . , c.sub.6.sup.1=001 100 are stored in the memory cells 302 at the address 1010, and the memory cells 303 at the address 1010 remain in the state 0.

(196) The block of the data bits [x.sub.1,x.sub.2]=[0,1] is transformed into the block of the data wits
[y.sub.1,y.sub.2,y.sub.3]=.sup.1([0,1])=[0,0,1]
and the block of the data bits [x.sub.3,x.sub.4]=[0,1] is transformed into the block of the data wits
[y.sub.4,y.sub.5,y.sub.6]=.sup.1([0,1])=[0,0,1]

(197) Since the data wits y.sub.1, . . . , y.sub.6=001 001 are intended to be stored at the address 1011, the check bits c.sup.1=c.sub.1.sup.1, . . . , c.sub.6.sup.1 result as
c.sub.1.sup.1, . . . ,c.sub.6.sup.1=(001 001 1011).Math.P.sub.10,6=101 011.

(198) The data wits y.sub.1, . . . , y.sub.6=001 001 are stored in the memory cells 301 at the address 1011. The check bits c.sub.1.sup.1, . . . , c.sub.6.sup.1=101 011 are stored in the memory cells 302 at the address 1011, and the memory cells 303 at the address 1011 remain in the state 0.

(199) If, in the course of the intention of wanting to access the data stored at the address 1010, an address error occurs by virtue of the address 1010, being corrupted to 1011 e.g. as a result of an error within the memory, the data stored at the address 1011 are read out, even though the data stored at the address 1010 should have been read out. In the present case, therefore, the check bits c.sub.1.sup.1, . . . , c.sub.6.sup.1=101 011 and the data wits y.sub.1, . . . , y.sub.6=001 001 are read out. The latter are supplemented by the address bits 1010 of the address which would have been accessed without errors in the memory. This results in the code word:
c.sub.1.sup.1, . . . ,c.sub.6.sup.1,y.sub.1, . . . ,y.sub.6,a.sub.1, . . . ,a.sub.4=101 011 001 001 1010.

(200) On account of the relationship
s.sup.T=H.Math.[101 011 001 001 1010].sup.T=[001110].sup.T0|
this code word is not a code word of the code C under consideration. The vector s.sup.T=[001110] is identical to the 16-th column of the H-matrix, which indicates an address error that is not corrected.

(201) In the example shown here, the code word has a length of 16 bits. The 6 check bits (cf. memory cells 302) and the 6 data wits (cf. memory cells 301) form a subset of the 16 bits of this code word.

(202) A subset of a set can be a proper subset of a set or the set itself.

(203) In the example just considered, the 6 first check bits c.sub.1.sup.1, . . . , c.sub.6.sup.1, the 6 data wits y.sub.1, . . . , y.sub.6 and the 4 address bits a.sub.1, . . . , a.sub.4, provided that no error occurs, form a code word of the used code of length 16. The 6 first check bits c.sub.1.sup.1, . . . , c.sub.6.sup.1 and the 6 data wits y.sub.1, . . . , y.sub.6 form a proper subset of the 16 bits of the set of all bits of a code word.

(204) In the case where the address is not included in the coding, the totality of the check bits and data wits represents all bits of a code word whose subset is identical to the set of all bits of the code word.

Example: Taking Account of Bits Derived from Address Bits

(205) An explanation is given of how e.g. instead of address bits a.sub.1, . . . , a.sub.n, bits A.sub.1, . . . , A.sub.i derived from the address bits can be taken into account in the formation of the check bits.

(206) By way of example, the bits A.sub.1, . . . , A.sub.i derived from the address bits a.sub.1, . . . , a.sub.m can be determined in accordance with

(207) $A_{1} =_{1} (a_{1}, .Math., a_{m}), .Math.$ $A_{l} =_{l} (x_{1}, .Math., a_{m}),$
wherein .sub.1, . . . , .sub.l are m-digit Boolean functions. By way of example, consideration is given below to the case in which lm holds true; however, it is also possible for l>m to hold true.

(208) In this regard, in accordance with one exemplary embodiment where l=1 and A.sub.l=A.sub.1, it is possible to use the following Boolean function:
A.sub.1=a.sub.1a.sub.2 . . . a.sub.n,
wherein denotes an exclusive-OR function. In this example, A.sub.1 identifies the parity of the address bits. By way of example, for m=4, the following results:
A.sub.1=.sub.1(a.sub.1, . . . ,a.sub.4)=a.sub.1a.sub.2a.sub.3a.sub.4.

(209) Each 1-bit error in the address bits a.sub.1, . . . , a.sub.4 thus leads to an error in the derived bit A.sub.1.

(210) In another exemplary embodiment it is possible that l=3 and the derived bits A.sub.1, . . . , A.sub.3 can be determined as follows:
A.sub.1=.sub.1(a.sub.1, . . . ,a.sub.4)=a.sub.3a.sub.4,
A.sub.3=.sub.2(a.sub.1, . . . ,a.sub.4)=a.sub.2a.sub.4,
A.sub.3=.sub.3(a.sub.1, . . . ,a.sub.4)=a.sub.1a.sub.4,
such that each 2-bit error in the address bits a.sub.1, . . . , a.sub.4 leads to a different value in the derived address bits A.sub.1,A.sub.2,A.sub.3. The Boolean functions .sub.1,.sub.2,.sub.3 are linear here by way of example.

(211) Alternatively, the derived bits could be determined as follows:
A.sub.1=.sub.1(a.sub.1, . . . ,a.sub.4)=a.sub.3a.sub.4 custom character ,
A.sub.2=.sub.2(a.sub.1, . . . ,a.sub.4)=a.sub.2a.sub.4(a.sub.1a.sub.2a.sub.3a.sub.4),
A.sub.3=.sub.3(a.sub.1, . . . ,a.sub.4)=a.sub.1a.sub.4,

(212) In this example, the Boolean functions .sub.1 and .sub.2 are nonlinear and the Boolean function .sub.3 is linear.

Example: Including the Bits Derived from the Address Bits in the Formation of the Check Bits

(213) An explanation is given below of how the bits A.sub.1, . . . , A.sub.l derived from the address bits can be included in the formation of the check bits.

(214) In the following example l=1 holds true and the derived address bit A.sub.1 is the parity bit of the bits of the addresses.

(215) The two blocks [x.sub.1,x.sub.2], [x.sub.3,x.sub.4] of useful data bits are transformed into two blocks of useful data wits [y.sub.1,y.sub.2,y.sub.3],[y.sub.4,y.sub.5,y.sub.6] in accordance with the WOM code of the table above, depending on the states contained in the corresponding memory cells prior to writing.

(216) FIG. 4 illustrates a memory area having an address 404 having the value 1010, for example, and 6 memory cells 401 for data wits (memory cells Z.sup.1, . . . ,Z.sup.6), 6 memory cells 402 for first check bits c.sup.1=c.sub.1.sup.1, . . . , c.sub.6.sup.1 (memory cells Z.sup.7, . . . , Z.sup.12) and 6 memory cells 403 for second check bits c.sup.2=c.sub.1.sup.2, . . . , c.sub.6.sup.2 (memory cells Z.sup.13, . . . , Z.sup.18).

(217) The two blocks of data wits [y.sub.1,y.sub.2,y.sub.3] and [y.sub.4,y.sub.5,y.sub.6] can be stored at the address a 404.

(218) The first check bits c.sup.1=c.sub.1.sup.1, . . . , c.sub.6.sup.1 are determined with the inclusion of the derived address bits, here the parity
A.sub.1=a.sub.1a.sub.2a.sub.3a.sub.4
of the address bits a.sub.1, . . . , a.sub.4, such that it holds true that
c.sup.1=c.sub.1.sup.1, . . . ,c.sub.6.sup.1=(.sup.i.sup.1,1([x.sub.1,x.sub.2]),.sup.i.sup.1,2([x.sub.3,x.sub.4]),A.sub.1).Math.P.sub.7,6,(29)
wherein the functions .sup.i.sup.1,1 and .sup.i.sup.1,2 are the functions that transform the useful data bits x.sub.1, . . . , x.sub.4 of the blocks [x.sub.1,x.sub.2],[x.sub.3,x.sub.4] into the corresponding blocks of data wits in accordance with the WOM code depending on the occupancy of the memory cells Z.sup.1,Z.sup.2,Z.sup.3 and Z.sup.4,Z.sup.5,Z.sup.6.

(219) As an example of a linear code C, use is made of a code having the G-matrix

(220) $\begin{matrix} G = (\begin{matrix} 1 & 1 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 1 & 1 & 0 & 1 & 0 & 0 & 0 & 0 & 0 \\ 1 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 \\ 0 & 1 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\ 1 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 \\ 0 & 1 & 1 & 0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 & 1 & 0 \\ 1 & 0 & 0 & 0 & 1 & 1 & 0 & 0 & 0 & 0 & 0 & 0 & 1 \end{matrix}) = (P_{7, 6}, I_{7}) & (30) \end{matrix}$
where

(221) $\begin{matrix} P_{7, 6} = (\begin{matrix} 1 & 1 & 1 & 0 & 0 & 0 \\ 0 & 0 & 0 & 1 & 1 & 1 \\ 1 & 0 & 1 & 1 & 0 & 0 \\ 0 & 1 & 0 & 0 & 1 & 1 \\ 1 & 0 & 0 & 1 & 1 & 0 \\ 0 & 1 & 1 & 0 & 0 & 1 \\ 1 & 0 & 0 & 0 & 1 & 1 \end{matrix}) & (31) \end{matrix}$

(222) By way of example, if all memory cells Z.sup.1, . . . , Z.sup.6 are in the state 0 before the first write operation, it holds true that .sup.i.sup.1,1=.sup.i.sup.1,2=.sup.1.

(223) In one example, in the first write operation, the intention is to store the blocks [x.sub.1,x.sub.2]=[1,0] and [x.sub.3,x.sub.4]=[1,1] at the address 1010 coded as data wits. From the address bits, the parity bit A.sub.1 results as:
A.sub.1=1010=0.

(224) It shall be assumed again that all memory cells are in the state 0 before the first write operation.

(225) The block of the data bits [x.sub.1,x.sub.2]=[1,0] is transformed into the block of the data wits
[y.sub.1,y.sub.2,y.sub.3]=.sup.1([1,0])=[1,0,0]
and the block of the data bits [x.sub.3,x.sub.4]=[1,1] is transformed into the block of the data wits
[y.sub.4,y.sub.5,y.sub.6]=.sup.1([1,1])=[0,1,0]

(226) Since the data wits y.sub.1, . . . , y.sub.6=100 010 are intended to be stored with the parity bit A.sub.1=0 at the address 1010, the check bits c.sup.1=c.sub.1.sup.1, . . . , c.sub.6.sup.1 result as
c.sub.1.sup.1, . . . ,c.sub.6.sup.1=(100 010 0).Math.P.sub.7,6=011 110.

Example: Inclusion of Indicator Bits

(227) It is also an option to take account of indicator bits i.sub.1, . . . , i.sub.L where L>0 in the formation of the check bits.

(228) In this case, indicator bits can form a password, for example, which is to be specified by a user when accessing the data. If the specified password is erroneous, an error can be indicated. In particular, the error can block outputting of the data. In another option, data are provided to different users from a memory via a data bus, wherein each user can only process the data which correspond to said user's own indicator bits or are filtered by means of said indicator bits.

(229) By way of example, let there be a code C having the code distance 3 and the H-matrix H=(l.sub.6,P.sub.6,10.sup.T) in accordance with equation (25), the G-matrix G=(P.sub.10,6,l.sub.10) in accordance with equation (26) and the parity matrix P.sub.10,6 in accordance with equation (27)

(230) All columns of the H-matrix have an odd number of ones, such that the code is a shortened Hsiao code. This Hsiao code allows all 1-bit errors to be corrected and all 2-bit errors to be detected.

(231) By way of example, two blocks of data bits [x.sub.1,x.sub.2] and [x.sub.3,x.sub.4] are coded into two blocks [y.sub.1,y.sub.2,y.sub.3] and [y.sub.4,y.sub.5,y.sub.6] of data wits in accordance with the WOM code specified by way of example here.

(232) The check bits c.sup.1=c.sub.1.sup.1, . . . , c.sub.6.sup.1 are determined with the inclusion of the indicator bits i=i.sub.1, . . . , i.sub.4 as follows
c.sup.1=c.sub.1.sup.1, . . . ,c.sub.6.sup.1(.sup.i.sup.1,1([x.sub.1,x.sub.2]),.sup.i.sup.1,2([x.sub.3,x.sub.4]),i.sub.1, . . . ,i.sub.4).Math.P.sub.10,6,(32)
wherein the explanations above correspondingly hold true for the functions .sup.i.sup.1,1, .sup.i.sup.1,2.

(233) In accordance with one example, in the first write operation, the intention is to store the blocks [x.sub.1,x.sub.2]=[1,0] and [x.sub.3,x.sub.4]=[1,1] at the address 1000 and the blocks [x.sub.1,x.sub.2]=[0,1] and [x.sub.3,x.sub.4]=[0,1] at the address 1001 coded as data wits. It shall again be assumed that all memory cells are in the state 0 before the first write operation.

(234) The block of the data bits [x.sub.1,x.sub.2]=[1,0] is transformed into the block of the data wits
[y.sub.1,y.sub.2,y.sub.3]=.sup.1([1,0])=[1,0,0]
and the block of the data bits [x.sub.3,x.sub.4]=[1,1] is transformed into the block of the data wits
[y.sub.4,y.sub.5,y.sub.6]=.sup.1([1,1])=[0,1,0]

(235) Since the data wits y.sub.1, . . . , y.sub.6=100 010 are intended to be stored using the indicator bits 1010, the check bits c.sup.1=c.sub.1.sup.1, . . . , c.sub.6.sup.1 result as
c.sub.1.sup.1, . . . ,c.sub.6.sup.1=(100 010 1010).Math.P.sub.10,6=001 100.

(236) If the data at the address 1000 are intended to be read out and if a user incorrectly inputs the indicator bits 1001 instead of the indicator bits 1010 (that is to say an incorrect password), then no valid code word of the code C results from the data wits 100 010 read at the address 1000, check bits 001 100 and the incorrect indicator bits 1001. The outputting of the data wits can be prevented, e.g. blocked, in this case.

Example: Inversion of Data Bits

(237) It is also an option to invert data bits before they are coded as data wits. In this case, at least one inversion bit is added to the data bits, wherein for example the data bits and the at least one inversion bit are coded jointly into data wits.

(238) It is also possible to assign a subset of useful data bits to at least one inversion bit, wherein the useful data bits of the subset of the useful data bits which are assigned to the at least one inversion bit are not inverted if the inversion bit assumes a first value, and are inverted if the inversion bit assumes a second value different than the first value.

(239) Moreover, it is an option to provide and include a plurality of inversion bits. In this case, different subsets of useful data bits can be assigned to different inversion bits.

(240) Furthermore, it is a possibility to assign the same subset of useful data bits to a plurality of inversion bits.

(241) For explanation purposes, one inversion bit is added in the following example, to which inversion bit all the useful data bits are assigned as a subset of the useful data bits.

(242) FIG. 5a shows a memory area in which (for example after an erasure operation) not all memory cells at the address a=10011 were successfully erased.

(243) A memory area having an address 504 having the value 10011, for example, is shown. On the basis of this address 10011, 19 memory cells Z.sup.1, . . . , Z.sup.19 are addressed comprising 9 memory cells 501 for data wits (memory cells Z.sup.1, . . . , Z.sup.9), 5 memory cells 502 for first check bits c.sup.1=c.sub.1.sup.1, . . . , c.sub.5.sup.1 (memory cells Z.sup.10, . . . , Z.sup.14), and 5 memory cells 503 for second check bits c.sup.2=c.sub.1.sup.2, . . . , c.sub.5.sup.2 (memory cells Z.sup.15, . . . , Z.sup.19).

(244) After the incomplete (or erroneous) erasure operation, the memory cells Z.sup.1, Z.sup.9 and Z.sup.14 are in each case in the state 1, and the other memory cells are in the state 0.

(245) 5 data bits x.sub.1, . . . , x.sub.5 are intended to be written to the memory directly, i.e. in non-inverted fashion, or in inverted fashion as x.sub.1, . . . , x.sub.5.

(246) In this example, the data bits x.sub.1, . . . , x.sub.5 are supplemented by an inversion bit Inv.sub.1, the value of which indicates whether the data bits are coded into data wits directly or in inverted fashion and are written to the memory. In this case, the data bits are transformed into data wits directly or in inverted fashion jointly with at least one inversion bit. In particular, it is an option to add a plurality of inversion bits.

(247) Inv.sub.1=0 is intended to hold true if the data bits are not inverted.

(248) Inv.sub.1=1 is intended to hold true if the data bits are inverted.

(249) If Inv.sub.1=0, the data bits
x.sub.1, . . . ,x.sub.5,Inv.sub.1=0
are coded into data wits and the data wits are written to the memory. If Inv.sub.1=1,
x.sub.1, . . . ,x.sub.5,Inv.sub.1=1
are coded as data wits and the data wits are written to the memory.

(250) If Inv.sub.1=0, then the data bits and the inversion bit as 3 blocks
[x.sub.1,x.sub.2],[x.sub.3,x.sub.4],[x.sub.5,Inv.sub.1=0]
are coded into 9 wits
[y.sub.1,y.sub.2,y.sub.3],[y.sub.4,y.sub.5,y.sub.6],[y.sub.7,y.sub.8,y.sub.9]
in accordance with the WOM code according to the table above as follows:
[y.sub.1,y.sub.2,y.sub.3]=.sup.i.sup.1([x.sub.1,x.sub.2]),
[y.sub.4,y.sub.5,y.sub.6]=.sup.i.sup.2([x.sub.3,x.sub.4]),
[y.sub.7,y.sub.8,y.sub.9]=.sup.i.sup.3([x.sub.5,0]),
where i.sub.1,i.sub.2,i.sub.3{1,2}.
If Inv.sub.1=1, the data bits and the inversion bit as 3 blocks
[x.sub.1,x.sub.2],[x.sub.3,x.sub.4],[x.sub.5,Inv.sub.1=1]
are coded into 9 wits
[y.sub.1*,y.sub.2*,y.sub.3*],[y.sub.4*,y.sub.5*,y.sub.6*],[y.sub.7*,y.sub.8*,y.sub.9*]

(251) in accordance with the WOM code in the table above as follows:
[y.sub.1*,y.sub.2*,y.sub.3*]=.sup.i.sup.4([x.sub.1,x.sub.2]),
[y.sub.4*,y.sub.5*,y.sub.6*]=.sup.i.sup.5([x.sub.3,x.sub.4]),
[y.sub.7*,y.sub.8*,y.sub.9*]=.sup.i.sup.6([x.sub.5,1]),
where i.sub.4,i.sub.5,i.sub.6{1,2}.

(252) As an example, the following data bits are considered:
x.sub.1=0,x.sub.2=1,x.sub.3=1,x.sub.4=1,x.sub.5=1.

(253) Firstly, the inversion bit Inv.sub.1 is set to be equal to 0. In this case, however, it is not possible to transform all blocks [x.sub.1,x.sub.2], [x.sub.3,x.sub.4],[x.sub.5,0] into data wits by means of the function .sup.i.sup.1=.sup.i.sup.2=.sup.i.sup.3=.sup.1 since for example
.sup.1([x.sub.1,x.sub.2])=.sup.1(0,1)=y.sub.1,y.sub.2,y.sub.3=0,0,1
holds true and the memory cell Z.sup.1 in FIG. 5a already has the state 1 and the value y.sub.1=0 cannot be written to it.

(254) If the inversion bit Inv.sub.1 is set to be equal to 1, then the inverted data bits can be transformed into data wits and be written to the memory, without the need to overwrite a state 1 already present in the memory with the value 0: it is thus possible to code the inverted data bits [x.sub.1,x.sub.2]=[1,0] with the function
.sup.i.sup.4=.sup.1 as .sup.1(0,1)=1,0,0
as data wits y.sub.1*,y.sub.2*,y.sub.3* and to store them in the memory cells Z.sup.1,Z.sup.2,Z.sup.3. It is likewise possible to code the inverted data bits [x.sub.3,x.sub.4]=[0,0] with the function
.sup.i.sup.5=.sup.1 as .sup.1(0,0)=0,0,0
and to code the inverted bit x.sub.5 and the inversion bit Inv.sub.1 [x.sub.5,1]=[0,1] with the function
.sup.i.sup.6=.sup.1 as .sup.1(0,1)=0,0,1
and to write them to the memory cells Z.sup.4, . . . , Z.sup.9.

(255) FIG. 5b shows that the wits 100, 000 and 001 are stored in the memory cells 501.

(256) By virtue of the fact that, after the inversion of the data bits, all the inverted data bits and the inversion bit are transformed into data wits with the function .sup.1, the number of ones in the data wits is lower than if the function .sup.2 had been used at least once.

(257) Since only the function .sup.1 (and not the function .sup.2) was used for transforming bits into wits in the first write operation in this example, even though the memory had not been erased in an error-free manner before the first write operation, in the second write operation it is still possible to store arbitrary values of bits in the second write operation. This would not be possible if the function .sup.2 of the WOM code had already been required for the first write operation (on account of the existing erase errors).

(258) If at least one inversion bit is used, the check bits for a code C under consideration arise from

(259) the useful data bits,

(260) the at least one inversion bit,

(261) the occupancy (already present) of the memory cells to which the bits coded as wits are written, and

(262) if appropriate further bits, e.g.

(263) at least one address bit and/or

(264) at least one identifier bit.

(265) One individual inversion bit is taken as a basis by way of example below, for the sake of clarity. However, the approach presented here is also correspondingly applicable to a multiplicity of inversion bits.

(266) If the inversion bit is equal to 0, the useful data bits and the inversion bit Inv.sub.1=0 are transformed block by block into blocks of data wits in accordance with the WOM code used, depending on the states of the corresponding memory cells. The check bits are determined such that the data wits and the check bits form a partial word of the code C.

(267) If the inversion bit is equal to 1, the inverted useful data bits and the inversion bit Inv.sub.1=1 are transformed block by block into blocks of data wits in accordance with the WOM code used, depending on the states of the corresponding memory cells. The check bits are determined such that the data wits and the check bits form a partial word of the code C.

(268) It is also possible to use address bits or bits derived from address bits or indicator bits for forming the check bits. If address bits, bits derived from address bits or indicator bits are used when determining the check bits, it is not necessary to invert the address bits, the bits derived from address bits and/or the indicator bits if the inversion signal is equal to 1. It is an option to invert the address bits, the bits derived from the address bits and/or the indicator bits when determining the check bits if the inversion bit indicates that an inversion of the data bits was effected.

(269) In the following example, no address bits, bits derived from address bits or indicator bits are taken into account when determining the check bits, for the sake of better clarity.

(270) By way of example, the code C that is intended to be used is the linear code whose H-matrix is specified by equation (6), G-matrix by equation (7) and parity matrix by equation (8).

(271) In the example, the inversion bit Inv.sub.1=1, and the inverted data bits and the inversion bit 10 00 01 are transformed into the data wits 100 000 001, as described above.

(272) The check bits c.sub.1.sup.1, . . . , c.sub.5.sup.1 result as

(273) $\begin{matrix} c_{1}^{1}, .Math., c_{5}^{1} = (f^{1} ({\overline{x}}_{1}, {\overline{x}}_{2}), f^{1} ({\overline{x}}_{3}, {\overline{x}}_{4}), f^{1} ({\overline{x}}_{5}, 1)) .Math. P_{9, 5} = \\ = (100 000 001) .Math. P_{9, 5} = 11101. \end{matrix}$

(274) These check bits can be written to the memory cells Z.sup.10, . . . , Z.sup.14; the value of the memory cell Z.sup.14 previously occupied erroneously at 1 does not lead to a conflict here (cf. FIG. 5b).

(275) The data wits 100 000 001 and the check bits 11101 form the code word
11101 100 000 001
of the code C having the H-matrix according to equation (6). If an error occurs for example in the 7-th data with y.sub.7*, which error corrupts the value y.sub.7*=0 to y.sub.7*=1 then this results in an error syndrome
H.Math.(11101 100 000 101).sup.T=(01001).sup.T,
which is identical to the 12-th column of the H-matrix in accordance with equation (6).

(276) The initially erroneous wits and check bits 11101 100 000 101 are improved to the correct values 11101 100 000 001 on the basis of the error syndrome (01001).sup.T in the 12-th column of the H-matrix in accordance with equation (6), said correct values being transformed into the useful data bits 10 00 01 in accordance with the WOM code. Since the inversion bit, here the 6-th bit, is equal to 1, said useful data bits are inverted into 01 11 10 which should be stored.

(277) In particular, it is an advantage that the inversion bit, via the error correction of the data wits into which it is transformed jointly with the data bits, is included in the error correction and is protected against errors.

(278) It is possible to use a plurality of inversion bits Inv.sub.1, . . . , Inv.sub.q with q>1. By way of example, the following can be defined:

(279) Inv.sub.1=0, . . . , Inv.sub.q=0 if no inversion of the useful data bits is effected,

(280) and Inv.sub.1=1, . . . , Inv.sub.q=1 if an inversion of the useful data bits is effected before the wits are determined from the useful data bits and the inversion bits.

(281) The q inversion bits can be included in the formation of the wits, such that after the storage of the wits, after the read-out, after an error correction of the wits and after the inverse transformation into useful data bits and inversion bits, it is possible to check whether or not the inversion bits are identical among one another.

(282) If e.g. the number of inversion bits q=3, it is possible, in the case where not all 3 inversion bits are identical among one another, to determine the value of the inversion bits with high error tolerance by means of a voter (a decision component) having 3 inputs and an output.

(283) It is also possible to use at least one inversion bit for a respective subset of useful data bits. On the basis of this at least one inversion bit it is possible to determine whether the corresponding subset of useful data bits is inverted or not inverted. In this regard, by way of example, useful data bits x.sub.1, . . . , x.sub.64 can be supplemented by 4 inversion bits Inv.sub.1, Inv.sub.2, Inv.sub.3, Inv.sub.4 as follows:
x.sub.1, . . . ,x.sub.16,Inv.sub.1,x.sub.17, . . . ,x.sub.32,Inv.sub.2,x.sub.33, . . . ,x.sub.48,Inv.sub.3,x.sub.49, . . . ,x.sub.64,Inv.sub.4

(284) In this case, the inversion bits Inv.sub.1, Inv.sub.2, Inv.sub.3, Inv.sub.4 are included in the formation of the data wits and thus in the error correction by the code C used.

(285) Another option comprises using, in addition to inversion bits, address bits or bits derived from address bits for determining the corresponding check bits. It is likewise possible also to use identifier bits in addition to the inversion bits for forming check bits.

(286) Furthermore, in one variant, in addition to the inversion bits, not only address bits or bits derived from address bits but also identifier bits are used for forming check bits.

(287) Furthermore, nonlinear codes can be used instead of linear codes. By way of example, it is possible to determine the check bits from the wits and the additional bits using a Berger code.

(288) Exemplary Circuit Arrangement

(289) FIG. 6 shows an exemplary circuit arrangement comprising a WOM coding unit 601, an error coding unit 602 (comprising an error detecting unit and/or an error correcting unit), a multiplexer 603 and an addressable memory 604.

(290) The memory 604 has N memory cells 605 for storing N wits in two successive write operations at an address a, without the memory content having to be erased after the first write operation. Furthermore, the memory 604 comprises m memory cells 606 for storing m first check bits in a first write operation and m memory cells 607 for storing m second check bits in a second write operation. The value a of the current address is present at an address input 608.

(291) At a first input 609 of the WOM coding unit 601, said first input having a width of K.Math.n.sub.W bits, K blocks [x.sup.1], . . . , [x.sup.K] of here in each case n.sub.W bits are present, wherein K2 and n.sub.W2. Accordingly, K.Math.n.sub.W bits are present overall at the input 609.

(292) The WOM coding unit 601 transforms (or codes) the K blocks [x.sup.1], . . . , [x.sup.K] of in each case n.sub.W useful data bits into K blocks [y.sup.1], . . . , [y.sup.K] of here in each case N.sub.W useful data wits, that is to say into a total of N=K.Math.N.sub.W wits y. These wits are applied to an input 610 of the memory 604 and stored in the N memory cells 605 at the address a. Furthermore, the N wits from the WOM coding unit 601 are applied to an input 611 of the error coding unit 602, said input having a width of N bits.

(293) The error coding unit 602 forms, from the N wits y, present at its input 611, in accordance with the code C.sup.i used, a number of m check bits c.sub.1.sup.i, . . . , c.sub.m.sup.i that are output to a data input 612 of the multiplexer 603, said data input having a width of m bits. The multiplexer 603 has two outputs having a width of m bits in order to store the check bits provided by the error coding unit 602 either in the memory cells 606 as first check bits or in the memory cells 607 as second check bits. In this case, i=1 for the first write operation of the first check bits and i=2 stands for the second write operation of the second check bits.

(294) The first check bits generated by the error coding unit 602 for the first write operation are accordingly designated by c.sub.1.sup.1, . . . , c.sub.m.sup.1 and the second check bits for the second write operation are designated by c.sub.1.sup.2, . . . , c.sub.m.sup.2.

(295) For the first write operation, the multiplexer 603 receives a control signal s=1 via an input 615 and connects the data input 612 to a data output 613, such that the first check bits c.sub.1.sup.1, . . . , c.sub.m.sup.1 are present at m data inputs of m memory cells 606 at the address a and can be stored in said memory cells.

(296) For the second write operation, the multiplexer 603 receives a control signal s=2 via the input 615 and connects the data input 612 to a data output 614, such that the second check bits c.sub.1.sup.2, . . . , c.sub.m.sup.2 are present at m data inputs of m memory cells 607 at the address a and are stored in said memory cells.

(297) The formation of the wits by the WOM coding unit 601 is effected both depending on the blocksto be coded as witsof data bits fed via the input 609 and depending on the values of the states of the memory cells 605; the latter dependence is represented by a connection between the memory cells 605 and an input 616 of the WOM coding unit 601.

(298) In this example in accordance with FIG. 6, the check bits are written to the memory 604 directly and not in a manner coded as wits.

(299) Optionally, the address a for addressing the memory 604 can also be fed to an input 621 of the error coding unit 602. This embodiment is indicated as connection 620 in FIG. 6. The check bits can thus be formed depending on the N wits y and on the current address a by means of the error coding unit 602. In accordance with the example shown here, the error coding unit 602 can create the check bits c.sub.1.sup.i, . . . , c.sub.m.sup.i such that
y,a,c.sub.1.sup.i, . . . ,c.sub.m.sup.i
is a code word of the code C.sup.i, wherein i=1 stands for the first write operation and i=2 stands for the second write operation.

(300) A further option comprises the formation of the check bits c.sub.1.sup.i, . . . , c.sub.m.sup.i being dependent on bits derived from address bits and/or on (arbitrary, e.g. predefined or predefinable) identifier bits. In such a case, the error coding unit 602 has for example at least one further input (not illustrated in FIG. 6) for inputting the bits derived from the address bits and/or for inputting identifier bits. Moreover, an input can be provided via which identifier bits that are currently to be input and to be verified can be provided e.g. by a user or a program, such that it is possible to compare predefined identifier bits with identifier bits currently input or received. The comparison as to whether the identifier bits are correct is carried out by checking whether a code word is present.

(301) FIG. 7 shows a diagram of a circuit arrangement for correcting stored wits obtained possibly erroneously during read-out from the memory.

(302) from the memory 604, N wits y are read out from N memory cells 605 and in a first read operation m first check bits c.sup.1=c.sub.1.sup.1, . . . , c.sub.m.sup.1 in are read out from m memory cells 606 and in a second read operation m second check bits c.sup.2=c.sub.1.sup.2, . . . , c.sub.m.sup.2 are read out from m memory cells 607 at the address a.

(303) The wits and also the check bits can contain erroneous bits. The first check bits c.sup.1 are present at a data input 703 of a demultiplexer 701, said data input having a width of m bits, and the second check bits c.sup.2 are present at an input 704 of the demultiplexer 701, said input having a width of m bits.

(304) The demultiplexer 701 receives a control signal s.sup.DMUX via an input 706. If s.sup.DMUX 0, the input 703 is connected to an output 705 of the demultiplexer 701; if S.sup.DMUX 1, then the input 704 is connected to the output 705.

(305) The output 705 of the demultiplexer 701 is connected to an input 707 of a correction unit 702.

(306) The correction unit 702 provides at an output 708 an N-component correction vector
e.sup.c=e.sub.1.sup.c, . . . ,e.sub.N.sup.c
for correcting the possibly erroneous wits y=y.sub.1, . . . , y.sub.N The correction unit 702 furthermore has an input 709 which is connected to the memory cells 605 and receives the N wits via this connection.

(307) An XOR circuit 710 has two inputs 712 and 713 having a width of N bits and an output 714 having a width of N bits. The input 712 is connected to the memory cells 605 and the input 713 is connected to the output 708 of the correction unit 702. Via the output 714, the possibly erroneous wits y=y.sub.1, . . . , y.sub.N are XORed with the correction vector e.sup.c component by component to form the corrected wits
y.sup.cor=y.sub.1.sup.cor, . . . ,y.sub.N.sup.cor
such that it holds true that:
ye.sup.c=y.sub.1e.sub.1.sup.c, . . . ,y.sub.Ne.sub.N.sup.c=y.sup.cor.

(308) The corrected wits y.sup.cor are provided via the output 714 to a wits decoding unit 711. The wits decoding unit forms the corrected bits x.sup.cor block by block from the corrected wits y.sup.cor.

(309) For i=1, . . . , N, the bit c.sub.i.sup.cor=1 if the with y.sub.i is corrected, and the bit c.sub.i.sup.cor=0 if the with y.sub.i is not corrected.

(310) FIG. 8 shows an optional extension of the circuit arrangement from FIG. 7, wherein a marker (e.g. in the form of m successive bits having the value 1) can be used for selecting the check bits when reading out the wits and the check bits.

(311) The first check bits are read out from the memory cells 606 and are present at an input of an AND gate 801, said input having a width of m bits. At the output of the AND gate 801, said output having a width of 1 bit, the value 1 is thus provided if all m bits at the input of the AND gate 801 also have the value 1, that is to say if the first check bits are identical to the marker.

(312) The output of the AND gate 801 is connected to a first input of an OR gate 802, at the second input of which the value 0 is present. An output of the OR gate 802 is connected to the input 706 of the demultiplexer 701.

(313) If the first check bits are not identical to the marker, that is to say

(314) $c^{1} \underset{m}{\underset{}{1, .Math., 1,}}$

(315) then the control value 0 is present at the input 706 of the demultiplexer 701. By contrast, if the first check bits correspond to the marker, that is to say

(316) $c^{1} = \underset{m}{\underset{}{1, .Math., 1,}}$
then the control value 1 is present at the input 706.

(317) The demultiplexer 701 connects the input 703 to the output 705 if the control value 0 is present, and it connects the input 704 to the output 705 if the control value 1 is present.

(318) Consequently, the first possibly erroneous check bits c.sup.1 are output at the output 705 by the demultiplexer 701 if the memory cells 606 are not occupied with the marker. By contrast, the second possibly erroneous check bits c.sup.2 are output at the output 705 if the memory cells 606 are occupied with the marker.

(319) By way of example, a memory arrangement can be provided which comprises a non-volatile memory for storing the first and second data wits y.sup.1 and y.sup.2 and for storing the corresponding first and second check bits c.sup.1 and c.sup.2. Moreover, the memory arrangement can for example additionally comprise a volatile memory for storing the first and second check bits c.sup.1 and c.sup.2 or for temporarily storing a copy of the first and second check bits c.sup.1 and c.sup.2. In this case it is possible to carry out, in a targeted manner, bit manipulations on the check bits stored in the volatile memory in the context of a system integration test, without the check bits stored in the non-volatile memory having to be altered.

(320) The volatile memory can comprise an SRAM or DRAM, for example. The non-volatile memory can be embodied e.g. as an EEPROM.

Error correction using WOM codes

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G06F11/1044

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G11C17/146

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G11C2029/4402

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G11C29/52

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G11C2029/0411

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G06F11/10

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G11C17/14

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G11C29/52

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G06F3/06

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Abstract

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