Shift register includes signal writing circuit, voltage control circuit and output circuit. The signal writing circuit is configured to write inverted signal of input signal provided by signal input terminal into second node responsive to control of second clock signal provided by second clock signal terminal. The voltage control circuit is configured to write first operating voltage into first node and write second clock signal into third node in voltage control circuit in response to control of voltage at first node, write second operating voltage into third node in response to control of second clock signal and write first clock signal provided by first clock signal terminal into first node in response to control of voltage at third node and first clock signal. The output circuit is configured to write second or first operating voltage into signal output terminal in response to control of voltage at first or second node.

Shift register includes signal writing circuit, voltage control circuit and output circuit. The signal writing circuit is configured to write inverted signal of input signal provided by signal input terminal into second node responsive to control of second clock signal provided by second clock signal terminal. The voltage control circuit is configured to write first operating voltage into first node and write second clock signal into third node in voltage control circuit in response to control of voltage at first node, write second operating voltage into third node in response to control of second clock signal and write first clock signal provided by first clock signal terminal into first node in response to control of voltage at third node and first clock signal. The output circuit is configured to write second or first operating voltage into signal output terminal in response to control of voltage at first or second node.

A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor.

According to one embodiment, an arithmetic device includes one or a plurality of arithmetic units. One of the one or plurality of arithmetic units includes a memory part including a plurality of memory regions, and an arithmetic part. At least one of the memory regions includes a memory element. The memory element is of a shift register-type.

The scanning line drive circuit has a configuration in which a plurality of unit circuits are connected in multiple stages. A unit circuit includes: a first transistor having a first conductive terminal to which a first-level voltage is applied and a second conductive terminal connected to a first node; a second transistor having a second conductive terminal to which a second-level voltage is applied; a third transistor having a first conductive terminal connected to the first node and a second conductive terminal connected to a first conductive terminal of the second transistor; a fourth transistor having a first conductive terminal connected to a control terminal of the third transistor, and having a second conductive terminal and a control terminal to both of which the second-level voltage is applied; and an output transistor having a control terminal connected to the first node and a second conductive terminal connected to an output terminal.

A shift register includes a first scan unit including a first input circuit and a first output circuit, and a second scan unit including a second input circuit, a second output circuit, and a potential boost circuit. The first input circuit is configured to transmit an input signal to a first pull-up node. The first output circuit is configured to, under a control of a voltage of the first pull-up node, output a shift signal and a first scan signal. The second input circuit is configured to transmit the input signal to a second pull-up node. The second output circuit is configured to output a second scan signal under a control of a voltage of the second pull-up node. The potential boost circuit is configured to boost the voltage of the second pull-up node in cooperation with the second output circuit.

An object is to provide a semiconductor device with improved operation. The semiconductor device includes a first transistor, and a second transistor electrically connected to a gate of the first transistor. A first terminal of the first transistor is electrically connected to a first line. A second terminal of the first transistor is electrically connected to a second line. The gate of the first transistor is electrically connected to a first terminal or a second terminal of the second transistor.

A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

A display panel, a stage circuit, and a driving method of the stage circuit are provided. The stage circuit includes cascaded shift register circuits. Each cascaded shift register circuit includes: a first control module, a second control module, and an output module. The first control module receives an input signal and a charging signal, and generates a voltage signal at a second node in response to a first clock signal and a voltage signal at a first node. With an exception of a first stage cascaded shift register circuit, a first transistor of a current stage cascaded shift register circuit has a first end connected to a signal output terminal of a previous stage cascaded shift register circuit, a second end connected to the second node, and a control end connected to the first node.

A shift register unit, a gate driving circuit, a display device, and a driving method are provided. The shift register unit includes a first input circuit, an output control circuit, and an output circuit. The first input circuit is configured to output a first input signal to a first node in response to a first control signal; the output control circuit is configured to output an output control signal to a second node under control of a level of the first node; and the output circuit includes an output terminal, and the output circuit is configured to output an output signal to the output terminal under control of a level of the second node.