The embodiments of the present disclosure provide a data transmission circuit, a display device and a data transmission method. The data transmission circuit includes a serial-to-parallel conversion circuit configured to receive serial data and a mode setting signal, generate a mode selection signal according to the mode setting signal, and convert the serial data into parallel data with a corresponding bit width according to the mode selection signal; a control signal generating circuit configured to generate a control signal based on the mode setting signal; and a latch circuit connected to the serial-to-parallel conversion circuit and the control signal generating circuit, and being configured to receive the parallel data from the serial-to-parallel conversion circuit and the control signal from the control signal generating circuit, and latch and output the received parallel data under the control of the control signal.

In a method of using an ultrasonic sensor comprising a two-dimensional array of ultrasonic transducers, a plurality of ultrasonic signals are transmitted according to a beamforming pattern at a position of the two-dimensional array. The beamforming pattern focuses the plurality of ultrasonic signals to location above the two-dimensional array, wherein the beamforming pattern identifies ultrasonic transducers of the two-dimensional array that are activated during transmission of the ultrasonic signals, and wherein at least some ultrasonic transducers of the beamforming pattern are phase delayed with respect to other ultrasonic transducers of the beamforming pattern. At least one reflected ultrasonic signal is received at the position according to a receive pattern, wherein the receive pattern identifies at least one ultrasonic transducers of the two-dimensional array that is activated during the receiving. The transmitting and the receiving are repeated at a plurality of positions of the two-dimensional array.

A shift register unit includes a shift drive sub-circuit, storing a voltage of a signal input terminal or outputting a voltage of a second clock signal terminal to a first signal output signal; an output sub-circuit, outputting a voltage of a first voltage terminal to a second signal output terminal; a pull-down sub-circuit, pulling down voltages of the first signal output terminal and the second signal output terminal to a second voltage terminal and a third voltage terminal.

Provided are a shift register unit and a driving method thereof, a scanning drive circuit, an array substrate and a display device, in the field of display technology. The shift register unit includes a shift registering circuit configured to provide a second clock signal from a second clock signal terminal to a first scanning output terminal under the control of a signal from a first scanning input terminal; an output circuit configured to provide a first level to a second scanning output terminal when the second scanning input terminal is at a first level and a first clock signal from the first clock signal terminal is at a first level; a first reset circuit configured to provide a second level to the second scanning output terminal after the second clock signal switches from the first level to the second level.

The present application discloses a method for preventing false output of a GOA circuit in a display panel. The method includes providing N clock signals respectively to N GOA units in each of M groups of GOA units cascaded in series. The N clock signals are outputted time-sequentially from a 1st clock signal to a N-th clock signal. The method additionally includes counting a first total number of pulses of the 1st clock signal and a second total number of pulses of the N-th clock signal, comparing each of them to M, and generating a reset signal based on a determination that at least one of the first total number of pulses and the second total number of pulses is smaller than M. The method furthermore includes releasing residual charges of the GOA circuit without outputting any gate-driving signal for a duration of time.

A display panel, a display device, and a drive method are provided. The display panel includes a plurality of sub-pixel units (40) arranged in an array and a gate drive circuit, and the array includes N rows. The gate drive circuit includes a plurality of cascaded shift register units and N+1 output terminals arranged in sequence, each of the plurality of cascaded shift register units is configured to output a gate scan signal for driving at least two rows of sub-pixel units in the N rows of the array to work; pixel drive circuits of an (n)-th row of sub-pixel units are connected to an (n)-th output terminal of the gate drive circuitto receive the gate scan signal as a scan drive signal, and sensing circuits of the (n)-th row of sub-pixel units are connected to an (n+1)-th output terminal of the gate drive circuit.

Examples include a fluidic die. The fluidic die may comprise an array of fluid actuators, an actuation data register, a mask register, and actuation logic. The actuation data register may store actuation data that indicates fluid ejectors to actuate for a set of actuation events. The mask register may store mask data that indicates a set of fluid actuators enabled for actuation for a respective actuation event of the set of actuation events. The actuation logic may electrically actuate a subset of the fluid actuators based at least in part on the actuation data register and the mask register for the respective actuation event.

A shift register and a method for driving the same, a gate driving circuit and a display apparatus are disclosed. The shift register includes: an input circuit configured to transmit an input signal from an input terminal to a first node; a first node control circuit configured to transmit a first voltage signal from a first voltage signal terminal to the first node; a second node control circuit configured to transmit a first clock signal from a first clock signal terminal to a second node; a third node control circuit configured to transmit a second voltage signal from a second voltage signal terminal to a third node; and an output circuit configured to transmit one of the first voltage signal from the first voltage signal terminal or the second voltage signal from the second voltage signal terminal to an output terminal.

A shift register is disclosed herein. The shift register includes a pull down circuit, a supplementary circuit, an output control circuit, and an input circuit. The supplementary circuit is coupled to the pull down circuit at a first node and a second node and is configured to receive a touch signal. The output control circuit is coupled to the second node. The input circuit is coupled to the first node and is configured to transmit an input voltage to the first node and the second node according to an input signal. The supplementary circuit transmits a voltage value of the touch signal to the second node according to the input voltage and the touch signal, so as to maintain a voltage value of the second node.

A gate on array (GOA) unit, a gate driver circuit, and a display device are provided. The GOA unit includes a driver circuit, a pull-down circuit, and a pull-down control circuit, the driver circuit is configured to output a first signal from an output end of the GOA unit. The pull-down circuit is connected with the driver circuit and at least one voltage end that provides a voltage signal, the pull-down circuit is configured to input the voltage signal into a control end of the driver circuit to drive the driver circuit to be in an off state when the GOA unit outputs an off signal. The pull-down control circuit is connected with the pull-down circuit and the driver circuit, and is configured to control the pull-down circuit to input the voltage signal to the control end of the driver circuit.