Patent classifications
G11C19/287
Shift register and method of driving the same, gate driving circuit, and display device
Some embodiments of the present disclosure provide a shift register and a method of driving the same, a gate driving circuit, and a display device. The shift register includes a first input sub-circuit for outputting a voltage on a first control voltage terminal to a pull-up node under control of a first signal input terminal; n output sub-circuits for outputting signal from output clock signal terminals to signal output terminals in sequence under control of the pull-up node; a first pull-down control sub-circuit for outputting a voltage on the first control voltage terminal to a pull-down node under control of a first clock signal terminal; a second pull-down control sub-circuit for pulling down a voltage on the pull-down node to a first voltage under control of the pull-up node; and a pull-down sub-circuit for pulling down a voltage on the pull-up node to the first voltage under control of the pull-down node.
Source driving sub-circuit and driving method thereof, source driving circuit, and display device
A source driving sub-circuit includes a shift register circuit and a latch circuit. The latch circuit includes a resetter and a latch. The resetter is coupled to an enabling signal terminal, a reset signal terminal and the latch. The latch is coupled to the shift register circuit and a data signal terminal. The latch is configured to receive signals output from the shift register circuit and at least in response to the signals output from the shift register circuit. And the resetter is configured to receive a signal provided from the enabling signal terminal and a signal provided from the reset terminal, and reset the at least one data signal latched by the latch in response to the signal provided from the enabling signal terminal.
MASK REGISTERS TO STORE MASK DATA PATTERNS
In some examples, a fluidic die includes a plurality of fluid actuators, an actuation data register to store actuation data that indicates each fluid actuator of the plurality of fluid actuators to actuate, and a plurality of mask registers to store respective different mask data patterns, each mask data pattern of the different mask data patterns indicating a respective set of fluid actuators of the plurality of fluid actuators enabled for actuation for a respective actuation event.
Display substrate and preparation method therefor, and display device
A display substrate, including: a display region and a peripheral region located on the periphery of the display region. A scan driver circuit is disposed in the peripheral region. A plurality of sub-pixels, and a plurality of first signal lines that are connected to the scan driver circuit and extend in a first direction, are disposed in the display region. The display region includes: a substrate, and a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer that are sequentially disposed on the substrate. The third conductive layer comprises: a plurality of first signal lines, and first electrodes and second electrodes of a plurality of transistors. An insulating layer between the third conductive layer and the first conductive layer is provided with first via holes.
Shift register unit and driving method thereof, driving apparatus and display apparatus
There is provided in the present disclosure a shift register unit, including: a pull-up control circuit, connected to a signal input terminal and a pull-up node; a pull-up circuit, connected to the pull-up node, a first clock signal terminal and a signal output terminal; a pull-down circuit, connected to a pull-down node, the pull-up node, the signal output terminal and a power supply voltage terminal, and configured to pull down voltages of the pull-up node and the signal output terminal to a voltage of the power supply voltage terminal under the control of the pull-down node; a first pull-down control circuit, connected to a second clock signal terminal, a pull-down control signal terminal, the pull-down node and the power supply voltage terminal, and configured to pull up the voltage of the pull-down node to a valid pull-down level under the control of the pull-down control signal terminal.
Shift register unit, driving method, gate drive circuit, and display device
A shift register unit, a driving method, a gate drive circuit and a display device are provided. The shift register unit includes: an input sub-circuit used to control an electric potential of the pull-up node, an output sub-circuit used to input a first clock signal from a first clock signal terminal to the output terminal, a pull-down control sub-circuit used to control an electric potential of the pull-down node, a pull-down sub-circuit used to control electric potentials of the pull-up node and the output terminal, a first reset control sub-circuit used to control an electric potential of the second control node under control of the first control node and a reset signal from the reset signal terminal and a reset sub-circuit used to control the electric potential of the pull-up node. The shift register unit improves the noise reduction efficiency at the output terminal.
Shift register, gate drive circuit, driving method thereof, and display device
The disclosure discloses a shift register, a gate drive circuit, a driving method thereof, and a display device, and the shift register includes: an input sub-circuit, an output sub-circuit, and an output control sub-circuit, where the input sub-circuit is configured to provide a signal of a first reference voltage signal terminal to a pull-up node under control of an input signal terminal; the output sub-circuit is configured to provide a signal of a clock signal terminal to a first signal output terminal under control of a potential of the pull-up node; and the output control sub-circuit is configured to provide a signal of the first signal output terminal to a second signal output terminal under joint control of an output control signal terminal, a third reference voltage signal terminal, and a fourth reference voltage signal terminal.
Array substrate, manufacturing method thereof, and display panel
An array substrate, a manufacturing method thereof and a display panel are provided. The array substrate includes a base substrate, a plurality of thin film transistors and a first light shielding layer. The base substrate includes a first surface and a second surface respectively located on opposite sides of the base substrate. The plurality of thin film transistors are disposed on the first surface of the base substrate, and each of the plurality of thin film transistors includes an active layer. The first light shielding layer is disposed on the second surface of the base substrate. The first light shielding layer has at least one opening that overlaps with at least one thin film transistor in a direction perpendicular to the second surface of the base substrate to allow light to irradiate at least the active layer of at least one thin film transistor.
Shift register unit and method for driving the same, gate driving circuit and display apparatus
A shift register unit and a method for driving the same, a gate driving circuit, and a display apparatus are disclosed. The shift register unit includes: an input circuit configured to transmit an input signal to a pull-up node; an output circuit configured to transmit a clock signal to an output signal terminal under control of a voltage at the pull-up node; a first reset circuit configured to reset the pull-up node to a first level under control of a first reset signal; a first pull-down control circuit configured to control levels at the pull-up node and the output signal terminal under control of a first control signal; and a first voltage control circuit electrically connected to a second control signal terminal, and configured to control a voltage signal waveform at the first pull-down node under control of a second control signal.
Shift register circuit and display panel using the same
A shift register comprises: a first switch electrically coupled to a control signal, and to a first node; a second switch electrically coupled to the first node, to a frequency signal, and to a first output signal; a third switch electrically coupled to a second node, to the first output signal, and to a low predetermined voltage level; a fourth switch electrically coupled to a second output signal, to the first node, and to the low predetermined voltage level; a fifth switch electrically coupled to the first node, to the frequency signal, and to a third node; and a pull-down control circuit electrically coupled to the frequency signal, the low predetermined voltage level and the second node.