An organic light emitting display comprises pixels connected to gate lines, and a gate driving circuit to supply a gate signal to at least one gate line, and having stages connected to each other in a cascading way. A n.sup.th (n is a positive integer) stage of the gate driving circuit includes a Q1 node charging unit to charge a Q1 node to a turn-on voltage using first and second clock signals in reverse-phase, and a pull-up transistor to apply the turn-on voltage to an output terminal in response to a Q1 node voltage. The Q1 node charging unit includes a first charging unit to charge the Q1 node voltage to the turn-on voltage using the second clock signal; and a second charging unit to charge a Q2 node, coupled to the Q1 node, using the first clock signal in a section where the Q1 node has the turn-on voltage.

A driving method, suitable for a display panel. The display panel includes a first display area, a second display area, a first gate driving circuit and a second gate driving circuit. The second display area comprises an opening. The driving method includes outputting a first gate signal to several first gate lines located at the first display area by the first gate driving circuit; outputting the first gate signal to several second gate lines located at the first display area by the second gate driving circuit, wherein the first gate lines and the second gate lines are arranged in an interlaced manner; outputting the first gate signal and a second gate signal to several third gate lines located at the second display area in the interlaced manner by the first gate driving circuit and the second gate driving circuit.

An electronic device, including an antenna, includes a pixel array, a control circuit, and a gate driver. The control circuit is coupled with the antenna, and configured to receive a RF signal from the antenna. The gate driver is coupled with the control circuit and the pixel array, and includes multiple shift registers. Each of the multiple shift registers is configured to output a scan signal to the pixel array. The control circuit is configured to output a triggering signal to a first-stage shift register of the multiple shift registers. When the control circuit receives the RF signal, the triggering signal has a triggering pulse. When the first-stage shift register receives the triggering pulse, the first-stage shift register outputs the scan signal having an enabling voltage level.

A shift register circuit is disclosed that includes an input control circuit configured to set a first node at a first potential in response to an active pulse signal from a signal input terminal, an output control circuit configured to supply a clock signal from a first clock signal terminal to a signal output terminal in response to the first node being at the first potential, the first potential being less than a potential of the active pulse signal and greater than or equal to a potential for maintaining operation of the output control circuit, and a reset circuit configured to supply a reference voltage from a reference voltage terminal to the first node and the signal output terminal in response to a reset signal.

A source driving sub-circuit includes a shift register circuit and a latch circuit. The latch circuit includes a resetter and a latch. The resetter is coupled to an enabling signal terminal, a reset signal terminal and the latch. The latch is coupled to the shift register circuit and a data signal terminal. The latch is configured to receive signals output from the shift register circuit and at least in response to the signals output from the shift register circuit. And the resetter is configured to receive a signal provided from the enabling signal terminal and a signal provided from the reset terminal, and reset the at least one data signal latched by the latch in response to the signal provided from the enabling signal terminal.

A shift register, a gate line driving method, an array substrate and a display device are provided. The shift register includes a plurality of shift register s arranged in a one-to-one correspondence with gate lines on an array substrate; and a control circuit configured to control signals outputted from the shift register s to the gate lines, to control each row of gate lines to be turned on and off, so that a display area has a high-resolution area and a low-resolution area. In the low-resolution area, the control circuit controls the gate lines to be turned on and off group by group. Each group of gate lines include at least two adjacent gate lines, and gate lines in the same group are turned on and off synchronously.

Examples include a fluidic die. The fluidic die may comprise an array of fluid actuators, an actuation data register, a mask register, and actuation logic. The actuation data register may store actuation data that indicates fluid ejectors to actuate for a set of actuation events. The mask register may store mask data that indicates a set of fluid actuators enabled for actuation for a respective actuation event of the set of actuation events. The actuation logic may electrically actuate a subset of the fluid actuators based at least in part on the actuation data register and the mask register for the respective actuation event.

A display device including: a display panel including a gate line and a data line; and a shift register including a stage for driving the gate line. The stage may include a first driving unit in a display area of the display panel and a second driving unit in a non-display area of the display panel.

A shift register and a display apparatus are provided. The shift register includes a pre-charge unit, a pull-up unit, a first pull-down unit and a second pull-down unit. The pre-charge unit receives first and second input signals, and outputs a pre-charge signal via a first node. The pull-up unit receives a pre-charge signal and a clock signal, and outputs a scanning signal via a second node. The first pull-down unit receives the pre-charge signal, first and second pull-down control signals, and controls whether to pull-down the scanning signal to a reference voltage level. The second pull-down unit receives the pre-charge signal, first and second pull-down control signals, and controls whether to keep the scanning signal at the reference voltage level. The duty cycle of the clock signal is less than 50 percent.

The present disclosure provides a driving circuit, a method for controlling light emission, and a display device. The driving circuit includes one or more light emission shift registers, each of which includes a first processing module configured to control a signal at a first node based on signals at the input signal terminal, the first clock signal terminal and the second clock signal terminal; a second processing module including first and second transistors, wherein the first transistor is a dual-gate transistor, and the second transistor has a first terminal electrically connected to the pulse signal terminal and a second terminal electrically connected to the second node; and an output module configured to control a signal at an output signal terminal based on the signals at the first level signal terminal, the second level signal terminal, the first node and the second node.