The present disclosure provides a driving circuit, a method for controlling light emission, and a display device. The driving circuit includes one or more light emission shift registers, each of which includes a first processing module configured to control a signal at a first node based on signals at the input signal terminal, the first clock signal terminal and the second clock signal terminal; a second processing module including first and second transistors, wherein the first transistor is a dual-gate transistor, and the second transistor has a first terminal electrically connected to the pulse signal terminal and a second terminal electrically connected to the second node; and an output module configured to control a signal at an output signal terminal based on the signals at the first level signal terminal, the second level signal terminal, the first node and the second node.

The present disclosure relates to a shift register unit, a driving method thereof, a gate driver on array and a display apparatus. The shift register unit includes a clock control circuit (10), an output control circuit (20) and an output circuit (30). The shift register unit may input clock signals of different frequencies or different duty ratios to the output control circuit (20) and the output circuit (30) respectively via the clock control circuit (10), such that the output circuit (30) can input driving signals of different frequencies or different duty ratios to the pixel units via the output end (OUT) in order to adjust the charging time for each line of pixel units. As a result, the driving manner of the display apparatus by the gate driver on array is enriched, and the driving flexibility is improved.

A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

A shift register unit is provided, which includes an input circuit, a first output circuit and a first output signal adjustment circuit. The input circuit is configured for receiving an input signal from an input terminal and controlling an electrical signal of a first node based on the input signal. The first output circuit is configured for outputting a first output signal at a first output terminal of the shift register unit based on a first clock signal under control of the electrical signal of the first node. The first output signal adjustment circuit is configured for providing a first reference signal to the first output terminal under control of the second clock signal so as to decrease an amplitude of the first output signal.

A shift register unit, a gate line driving device includes multiple stages of the shift register units, and a driving method for being applied to the shift register unit; the shift register unit includes: an input module connected between an input terminal and a pull-up node, and configured to charge the pull-up node; an output module connected between the pull-up node, a first clock signal terminal and an output terminal, and configured to output to the output terminal a first clock signal received at the first clock signal terminal; a pull-up node reset module connected between a reset terminal, a pull-down node and the pull-up node, and configured to reset the pull-up node; and an output reset module connected between a second clock signal terminal, the pull-down node and the output terminal, and configured to reset the output terminal.

Provided are a drive circuit and a display apparatus capable of making the waveforms of driving signals uniform. The drive circuit comprises a plurality of shift registers each comprising an input end, an output end, and a switching element connected between the input end and the output end. The input ends are respectively connected to a plurality of branch points on an input-signal line arranged on a display panel. The output ends are respectively connected to a plurality of output-signal lines. The drive circuit outputs a driving signal from the output end, on the basis of a signal input through the input end. All or some of the shift registers differ, according to a position of the branch point to which the input end is connected, in resistance value between the input end and the output end while the switching element is ON.

The present disclosure relates to a bidirectional shift register unit, a bidirectional shift register, and a display panel, wherein the bidirectional shift register unit includes: an pull-up circuit is configured to transform first clock signals into scanning signals outputting at a current level, an pull-up control circuit is configured with a forward pull-up sub-circuit and a backward pull-up sub-circuit respectively configured to pull up a potential of a control end of the pull-up circuit when a forward scanning process or a backward scanning process is conducted, a pull-down circuit and a pull-down maintaining circuit are respectively configured to pull down and continuously pull down the potential of the control end of the pull-up circuit and the scanning signals outputting at the current level during a pull-down phase. As such, a bidirectional scanning process may be achieved.

A gate driving circuit includes a shift unit and a switch unit. The shift unit receives a start input signal, a first clock input signal and a second clock input signal to generate an enable output signal. The switch unit is connected to the shift unit and receiving the enable output signal. The switch unit outputs a third clock signal based on the enable output signal.

Provided are a shift register unit and a driving method thereof, a scanning drive circuit, an array substrate and a display device, in the field of display technology. The shift register unit includes a shift registering circuit configured to provide a second clock signal from a second clock signal terminal to a first scanning output terminal under the control of a signal from a first scanning input terminal; an output circuit configured to provide a first level to a second scanning output terminal when the second scanning input terminal is at a first level and a first clock signal from the first clock signal terminal is at a first level; a first reset circuit configured to provide a second level to the second scanning output terminal after the second clock signal switches from the first level to the second level

A shift register unit, a method of driving a shift register unit, a gate driving circuit and a display device are provided. The shift register unit includes an input circuit, a first pull-up node reset circuit and an output circuit. The input circuit is configured to control an level of a pull-up node to a first level in response to an input signal of an input terminal, and thereafter control a level of a first node to a second level under control of a level of a pull-down node. The first node is in a current path for controlling the level of the pull-up node. The first pull-up node reset circuit is configured to reset the pull-up node in response to a first reset signal. The output circuit is configured to output a clock signal to an output terminal under control of the level of the pull-up node.