The present disclosure provides a GOA circuit, a method for driving the GOA circuit, and a display panel. The GOA circuit includes a plurality of GOA sub-circuits. Each GOA sub-circuit includes a plurality of cascaded shift register units. Each of the GOA sub-circuits is connected to an independent start signal terminal, and the start signals of different GOA sub-circuits are separated by a time interval for acquisition of touch signals.

The present disclosure proposes a shift register circuit and a method for driving the same, a gate driving circuit and a method for driving the same, and a display apparatus. The shift register circuit comprises an input circuit, a reset circuit, a control circuit and a multi-output circuit. The input circuit is configured to receive an input signal and output a signal to a first node based on the input signal; the reset circuit is configured to receive a reset signal and a first reference signal, and output the first reference signal to the first node under control of the reset signal; the control circuit is configured to control a potential at the first node to be an inverted potential of a potential at the second node; and the multi-output circuit is configured to receive the first reference signal and a plurality of clock signals, and output a plurality of driving signals according to the corresponding clock signals and the first reference signal under the control of signals at the first node and the second node.

The present disclosure provides a shift register, the register including n stages, each being configured for performing forward and reverse operations, wherein in the forward operation, a gate signal is output in a forward direction, wherein in the reverse operation, a gate signal is output in a reverse direction, wherein a n-th stage among the n stages includes: a charging unit configured for charging a Q node in a response to a reception of a forward start signal or a reverse start signal; a gate signal output unit configured for outputting a gate signal in a response to the Q node being charged by the charging unit; and a discharging unit configured for discharging the Q node after the output unit has outputted the gate signal, wherein the charging unit includes a dummy transistor and a reverse start transistor, both being connected to the Q node.

A shift register comprises: a first switch electrically coupled to a control signal, and to a first node; a second switch electrically coupled to the first node, to a frequency signal, and to a first output signal; a third switch electrically coupled to a second node, to the first output signal, and to a low predetermined voltage level; a fourth switch electrically coupled to a second output signal, to the first node, and to the low predetermined voltage level; a fifth switch electrically coupled to the first node, to the frequency signal, and to a third node; and a pull-down control circuit electrically coupled to the frequency signal, the low predetermined voltage level and the second node.

A shift register comprises: a first switch electrically coupled to a control signal, and to a first node; a second switch electrically coupled to the first node, to a frequency signal, and to a first output signal; a third switch electrically coupled to a second output signal, to the first output signal, and to a low predetermined voltage level; a fourth switch electrically coupled to a second node, to the first node, and to the low predetermined voltage level; a fifth switch electrically coupled to the first node, to the frequency signal, and to a third node; and a pull-down control circuit electrically coupled to the frequency signal, the low predetermined voltage level and the second node.

A shift register unit and a method of driving the same, a gate driving circuit and a display device are provided. The first pull-up circuit of the shift register is configured to output a signal of the first clock signal end to the first signal output end under a control of the pull-up node. The second pull-up circuit is configured to output the signal of the first clock signal end to the second signal output end under a control of the pull-up node. The first pull-down circuit is configured to pull down a potential of the pull-up node and a potential of the first signal output end to the potential of the second voltage end under a control of the pull-down node. The second pull-down circuit is configured to pull down a potential of the second signal output end to the potential of the second voltage end under a control of the pull-down node.

Embodiments of the present disclosure provide a pulse generation device, an array substrate, a drive circuit and a driving method. The pulse generation device includes: a reset module making a pulse output end output low level, in response to a low level of a first input end or in response to a low level of a second input end and a low level of a third input end; a pulse generation module making the pulse output end output a high level, in response to a high level of the first input end, a high level of the second input end and a low level of the third input end or in response to a high level of the first input end, a low level of the second input end and a high level of the third input end.

A reset circuit for compensating a level reduction at a first node during a first stage without affecting levels during a second stage includes a reset portion, a reset control portion, and at least three input terminals. The reset portion is coupled to the first and second input terminals, and a second node, and is configured to be turned on if the second node is at a first level, to electrically couple the second and first input terminals. The reset control portion is coupled to the first, second, and third input terminals, and the second node, and is configured to electrically couple the second input terminal with the second node if the first input terminal is at the first level, and to electrically couple the second node with the third input terminal if the second input terminal is at a second level.

There are disclosed in the present disclosure a shift register unit and a driving method thereof, a gate driving circuit, an array substrate and a display apparatus. The shift register unit includes: an input sub-circuit for receiving an input signal from an input terminal, outputting the input signal to the pull-up node, and outputting a pull-up signal through the pull-up node; a first output sub-circuit for receiving the pull-up signal and a first clock signal, and outputting a first output signal from a first output signal terminal according to the pull-up signal and the first clock signal; a second output sub-circuit for receiving the pull-up signal and a second clock signal, and outputting a second output signal from a second output signal terminal according to the pull-up signal and the second clock signal; a storage sub-circuit for storing the pull-up signal.

A shift register unit includes a first output control circuit, a first output circuit, a second output control circuit, a second output circuit, a reset circuit, and a node set circuit. The node set circuit is configured to periodically transfer a first voltage having an inactive level to a first node within the shift register unit during being enabled.