The present disclosure provides a shift register, a driving circuit, a display device and a driving method for improving the accuracy of an output signal. The first input unit of the shift register is configured to provide a signal at a first fixed potential terminal to a first node, a signal at the input signal terminal to the first node and the signal at the input signal terminal to the first node. A second input unit of the shift register is configured to provide the signal at the input signal terminal to the second node and a signal at the first fixed potential terminal to the second node. An output unit of the shift register is configured to provide a signal at the first clock signal terminal to an output signal terminal of the shift register and a signal at a second fixed potential terminal to the output signal terminal.

A display panel includes a display area, a non-display area surrounding the display area, and a plurality of signal lines, signal connection lines, and cascaded shift registers aligned in the non-display area. The display area includes a curved corner, and the non-display area includes a corner non-display area adjacent to the curved corner. The cascaded shift registers are electrically connected by associated cascade lines, and each cascaded shift register is connected with a corresponding signal line through an associated signal connection line. The associated cascade lines are located on a side of the cascaded shift registers away from the display area, and the signal lines are located on a side of the associated cascade lines away from the cascaded shift registers. The wiring directions of the signal lines and the extension lines of the associated cascade lines are in parallel with an outer edge of the non-display area.

A gate driving circuit is provided, which includes shift registers and a reset signal line. The shift registers respectively provide scan signals to gate lines of a display panel. Each shift register includes a precharge unit and pull-up unit. The precharge unit is coupled to a first node and outputs a precharge signal through the first node. The pull-up unit is coupled to the first node and the second node and outputs one of the scan signals to a corresponding one of the gate lines through the second node. The reset signal line is coupled to the shift registers and provides a reset signal to the shift registers. The reset signal is used to reset the shift registers after the shift registers respectively output the scan signals. The reset signal line is arranged between a layout area of the precharge unit and a layout area of the pull-up unit.

A shift register includes a first input circuit, a second input circuit, and a pull-up transistor. The first input circuit is coupled to a first input terminal and a first pull-up node, and configured to electrically connect the first input terminal to the first pull-up node when the first input terminal receives an active signal. The second input circuit is coupled to a second input terminal and a second pull-up node, and configured to electrically connect the second input terminal to the second pull-up node when the second input terminal receives an active signal. The pull-up transistor includes a first gate electrode coupled to the first pull-up node and a second gate electrode coupled to the second pull-up node.

The present application provides a shift register unit including: an input sub-circuit coupled to an input terminal, an first voltage terminal and an pull-up node; an output sub-circuit coupled to the pull-up node and art first clock terminal; a first storage sub-circuit having two terminals respectively coupled to the pull-up node and an output terminal; a first reset sub-circuit coupled to an reset terminal, an second voltage terminal, the pull-up node and the output terminal; a second reset sub-circuit coupled to a second clock terminal and a pull-down node; a pull-down sub-circuit coupled to the pull-down node, the second voltage terminal and the output terminal; and a spacing sub-circuit coupled to the pull-up node, the pull-down node and the second voltage terminal. The present application further provides a driving method of a shift register unit, a gate driving circuit and a display device.

A shift register unit, a driving method, a gate drive circuit and a display device are provided. The shift register unit includes: an input sub-circuit used to control an electric potential of the pull-up node, an output sub-circuit used to input a first clock signal from a first clock signal terminal to the output terminal, a pull-down control sub-circuit used to control an electric potential of the pull-down node, a pull-down sub-circuit used to control electric potentials of the pull-up node and the output terminal, a first reset control sub-circuit used to control an electric potential of the second control node under control of the first control node and a reset signal from the reset signal terminal and a reset sub-circuit used to control the electric potential of the pull-up node. The shift register unit improves the noise reduction efficiency at the output terminal.

A display panel including a pixel array, a plurality of first shift registers, a plurality of second shift registers, a plurality of first discharge circuits, and a plurality of second discharge circuits is provided. The pixel array includes a plurality of gate lines. The shift registers provide a plurality of gate signals to the gate lines. Each of the first discharge circuits receives a third gate signal to discharge a same first gate line together with the corresponding first shift register. A rising edge of the third gate signal substantially matches a falling edge of the corresponding first gate signal. Each of the second discharge circuits receives a fourth gate signal to discharge a same second gate line together with the corresponding second shift register. A rising edge of the fourth gate signal substantially matches a falling edge of the corresponding second gate signal.

A shift register unit provided according to embodiments of the present disclosure includes an input circuit, a pull-up circuit, a control circuit, and a first discharge circuit. The pull-up circuit is configured to control an output of the signal output terminal. The control circuit is configured to control a potential of the second node based on a second voltage signal of the second voltage terminal and a potential of the first node. The first discharge circuit is configured to control, after being turned on under the control of the potential of the second node, the first node and the signal output terminal by using the third voltage terminal, and discharging a pixel unit, the first node and the signal output terminal, the pixel unit being connected to the signal output terminal.

An array substrate, a display panel, a display device and a driving method. The array substrate includes: a plurality of first pixel units arranged in an array in a first region; a first gate driving circuit a second gate driving circuit; a plurality of first gate lines connected with the first gate driving circuit; and a plurality of second gate lines connected with the second gate driving circuit. A first portion of the plurality of first pixel units is connected with the plurality of first gate lines, and each first pixel unit in the first portion is connected with one of the plurality of first gate lines; and a second portion of the plurality of first pixel units is connected with the plurality of second gate lines, and each first pixel unit in the second portion is connected with one of the plurality of second gate lines.

A display panel includes a shift register and an active terminator. The shift register has a drive circuit coupled to one end of a gate line. The active terminator is coupled to the other end of the gate line and includes a first transistor, a second transistor, and a first capacitor. The first transistor has a first terminal connected to a first clock signal, a second terminal connected to the gate line, and a third terminal. The second transistor has a first terminal connected to a first internal node, a second terminal connected to the third terminal of the first transistor, and a third terminal connected to a first DC voltage source. The first capacitor has a first terminal connected to the gate line and a second terminal connected to the third terminal of the first transistor and the second terminal of second transistor.