A scan driver that includes a plurality of stages of scan driving circuits is provided. Each scan driving circuit includes: a driving transistor, including: a control terminal configured to receive a current-stage scan control signal, a first terminal configured to receive a first clock signal, and a second terminal configured to output a current-stage scan signal; an input stage circuit coupled to the driving transistor, where the input stage circuit includes: a first input transistor and a second input transistor, the first input transistor includes: a control terminal, a first terminal, and a second terminal, the second input transistor includes: a control terminal, a first terminal, and a second terminal, the control terminal of the first input transistor is configured to receive a next-stage scan signal, the control terminal of the second input transistor is configured to receive a previous-stage scan signal, and the second terminal of the first input transistor and the second terminal of the second input transistor are coupled to the control terminal of the driving transistor; a pull-down circuit, coupled to the driving transistor and configured to pull down the current-stage scan control signal and the current-stage scan signal; and a capacitor, coupled to the driving transistor and configured to maintain the current-stage scan control signal, where in a first scan mode, the first terminal of the first input transistor receives the first clock signal, and the first terminal of the second input transistor receives a first scan direction control signal; and in a second scan mode, the first terminal of the first input transistor receives a second scan direction control signal, and the first terminal of the second input transistor receives the first clock signal.

A display panel includes a plurality of scan lines and a scan driving circuit for driving the plurality of scan lines, where each of the plurality of scan lines extending in a first direction and sequentially aligned in a second direction, and the first direction intersects with the second direction; the scan driving circuit includes a first scan driving sub-circuit, a second scan driving sub-circuit, and a third scan driving sub-circuit, and the first scan driving sub-circuit is cascaded with the second scan driving sub-circuit; and the display panel includes a first area and a second area adjacent to each other in the second direction, the first scan driving sub-circuit drives scan lines in the first area in a progressive scan mode, and the second scan driving sub-circuit and the third scan driving sub-circuit respectively drive scan lines in the second area in an interlaced scan mode.

The present disclosure describes a shift register unit, an organic light-emitting display panel and a driving method. The shift register unit comprises a node potential controller and an output unit. The node potential controller comprises a first output end and a second output end. The output unit is configured to output, based on a first control signal from the first output end and a second control signal from the second output end, a first level signal or a second level signal. According to the solutions provided by the application, the potential of each node in the shift register unit is stable and controllable, and contributed to the avoidance of output logic execution problem in the shift register unit caused by unstable node potential when each control signal level of the shift register unit jumps.

An output control node stabilization portion includes a thin film transistor having a gate terminal to which is provided a fourth clock that changes to an on level at timing at which a scanning signal outputted from a previous stage is to change from an off level to an on level, a drain terminal connected to an output control node, and a source terminal to which the scanning signal outputted from the previous stage is provided; and a thin film transistor having a gate terminal to which is provided a third clock that changes to an on level at timing at which a scanning signal outputted from a subsequent stage is to change from an off level to an on level, a drain terminal connected to the output control node, and a source terminal to which the scanning signal outputted from the subsequent stage is provided.

A shift register, a gate driving circuit, a display panel and a driving method. The shift register includes: an input circuit, an output circuit, a pull-up-node pull-down circuit, a first control circuit, a second control circuit and an output pull-down circuit. The first control circuit is configured to write a fourth clock signal into a first pull-down node and write a first power voltage into a second pull-down node responsive to a first control signal, and to write the first power voltage into the first pull-down node responsive to a voltage of a pull-up node. The second control circuit is configured to write the fourth clock signal into the second pull-down node and write the first power voltage into the first pull-down node responsive to a second control signal, and to write the first power voltage into the second pull-down node responsive to the voltage of the pull-up node.

A shift register unit is provided. The shift register unit includes a precharging module, a resetting module, a pull-up control module and a noise reduction module. The precharging module is connected to the resetting module and a pull-up node, the resetting module is connected to the pull-up node, the noise reduction module and an output end, the pull-up control module is connected to the pull-up node, the noise reduction module and the output end, and the noise output module is connected to the output end.

The embodiments of the present disclosure propose a shift register, a driving method thereof, a gate driving circuit and a display apparatus. The shift register comprises an input sub-circuit coupled to an input terminal and a pull-up node, and configured to charge the pull-up node under control of an input signal from the input terminal; an output sub-circuit coupled to a clock signal terminal, the pull-up node, and an output terminal, and configured to transmit a clock signal from the clock signal terminal to the output terminal under control of the pull-up node; and an output shaping sub-circuit coupled to the clock signal terminal, the output terminal, and a first voltage signal terminal, and configured to transmit a first voltage signal from the first voltage signal terminal to the output terminal under control of the clock signal.

Provided are a display panel including a scan driver and a method of operating the same. The display panel includes a shift register including a plurality of stages that shifts and outputs a clock signal. A display area in the display panel is divided into a plurality of driving areas. The stages of the shift register corresponding to each driving area form a stage group. In each stage group, the stages included in the stage group sequentially output a scan signal by using an independent start signal.

A shift register, a gate drive circuit, a display apparatus and a driving method of the shift register are provided. The shift register includes an input subcircuit, a first and a second output subcircuits, a trigger signal input terminal, a first and a second signal output terminals, a first and a second clock terminals and a pull-up node, a control terminal and an output terminal of the input subcircuit are electrically coupled to the trigger signal input terminal and the pull-up node, respectively, for providing a valid signal received by the control terminal of the input subcircuit to the pull-up node. The shift register is provided with the first and second output subcircuits which share the same input subcircuit, greatly reducing the number of devices and thus greatly simplifying the structure of the cascaded shift registers and reducing the area of the whole display apparatus.

A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings.