A shift register unit and a driving method thereof, a gate driving circuit and a display apparatus. The shift register unit includes an input circuit, a first pull-down circuit, a second pull-down circuit, and an output circuit. In a first state, the first pull-down circuit is configured to pull down the level of a pull-up node, and the second pull-down circuit is configured to pull down a level of the output terminal.

There is disclosed a shift register unit, a gate driving circuit and a display device. The shift register unit includes a shift register module configured to delay a phase of a signal from the input terminal, and output the delayed signal at the first output terminal; a first input module configured to set the first node to be at a second voltage level; a second input module configured to set the first node to be at the first voltage level, and apply the signal from the input terminal to the first node; and an output module configured to set the second output terminal to be at the second voltage level when the first output terminal is at the first voltage level, and set the second output terminal to be at the first voltage level when the first node is at the first voltage level.

The present disclosure provides a shift register unit, which includes an input circuit, a reset circuit, a noise reduction circuit, and an output circuit. The input circuit is configured to control a voltage of a first node based on a first input signal and a second input signal, and control a voltage of a second node based on a first voltage and the voltage of the first node. The reset circuit is configured to reset the voltage of the first node and the voltage of the second node. The noise reduction circuit is configured to maintain a reset voltage of the first node and a reset voltage of the second node. The output circuit is configured to provide, for an output terminal of the output circuit, a second clock signal from a second clock signal terminal or the second voltage. The shift register unit is composed of switch elements.

A display device includes a first substrate and a second substrate opposite to each other, a gate line on the first substrate, a gate driver which is connected to the gate line, a clock line which transmits a clock signal, a connecting line which connects the clock line and the gate driver, a common electrode on the second substrate, the common electrode overlapping the clock line and the connecting line, and a compensation pattern which overlaps the common electrode and extends from the connecting line.

A first flipflop outputs a first signal synchronized with a first clock signal, a second flipflop outputs a second signal synchronized with a second clock signal, and a third flipflop outputs a third signal synchronized with a third clock signal. The second flipflop includes first to third transistors. In the first transistor, the second clock signal is input to a first terminal and the second signal is output from a second terminal. In the second transistor, a first signal is input to a first terminal, a second terminal is electrically connected to a gate of the first transistor, and the first clock signal is input to a gate. In the third transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the first transistor, and the third clock signal is input to a gate.

A scan driving circuit and a device are disclosed. The scan driving circuit has a plurality of scan driving units coupled in cascade. A (N)-cascaded scan driving unit includes a first control module, a second control module, and an output module. The second control module includes a first switch unit, a second switch unit, a potential holding unit and a first switch control unit. A control end of the second switch unit receives the (N-1)-stage scanning signal, the first switch control unit is configured for controlling the first switch unit, according to the second clock signal, the (N-1)-stage scanning signal, and the first constant voltage signal passed through the second control end of the first switch unit, to control the first switch unit, for operating that the first switch unit and the second switch unit are not conducted at the same time.

A circuit and an array circuit for implementing a shift operation are provided. The circuit for implementing a shift operation includes a resistive random-access memory and four switches. The circuit has a simple structure and can improve computational efficiency.

A GOA signal determining circuit and method thereof, gate driver circuit, and display device are provided. The GOA signal determining circuit is connected to an input end of a GOA unit, at least two clock signal ends of the GOA unit, and a control end of a reset unit of a PU node in the GOA unit. The GOA signal determining circuit detects a signal of the input end of the GOA unit and a signal of the at least two clock signal ends of the GOA unit, and outputs a control signal to the reset unit of the PU node to control the reset unit to output a reset signal to the PU node to turn off an output transistor of the GOA unit, upon determining both of the signal of the input end and the signal of the at least two clock signal ends are abnormal.

The present application discloses a gate driver on array (GOA) circuit including a first GOA circuit; a second GOA circuit; and a voltage transmitting circuit configured to transmit an output voltage from the first GOA circuit to the second GOA circuit as an input voltage for the second GOA circuit; the output voltage from the first GOA circuit and the input voltage for the second GOA circuit having a substantially the same voltage level. An input port of the voltage transmitting circuit is connected to an output port of the first GOA circuit and configured to receive the output voltage from the first GOA circuit; and an output port of the voltage transmitting circuit is connected to an input port of the second GOA circuit and configured to output a forwarded voltage to the second GOA circuit as the input voltage for the second GOA circuit.

A gate driving unit includes first to nth stages sequentially outputting first to nth gate pulses, respectively, according to a start signal, wherein n is an integer larger than 2; and a dummy stage receiving the nth gate pulse, charging an (n+1)th Q node and outputting a dummy pulse synchronized with a clock signal, the dummy stage receiving a reset signal and discharging the (n+1)th Q node, wherein the first to nth stages receive the reset signal and charge first QB to nth QB nodes, respectively.