The present disclosure provides a shift register unit comprising a first signal input terminal, a second signal input terminal, an input and reset module, a pull-up module, a pull-down module, a pull-down control module, a clock signal input terminal, a first level input terminal, a second level input terminal, a first voltage terminal, a second voltage terminal, a signal output terminal, a discharge module and a current leakage suppression module. The present disclosure further provides a gate driving circuit, a touch display device, and a method for driving a shift register unit. A phenomenon of dark lines does not occur during display on the touch display device.

The invention provides a gate driving circuit and a display device. The gate driving circuit is configured to drive a display panel of the display device, and includes shift registers and at least a dummy shift register. The shift registers are respectively configured to generate and output scan signals to scan lines of the display panel, the dummy shift register is configured to generate a dummy scan signal before the scan signals are generated. The dummy scan signal and the scan signals are sequentially generated.

Provided is a shift register, comprising an input circuit, an output circuit, and a control circuit, which are electrically connected to a control node. The input circuit is electrically connected with a signal input terminal of the shift register, and is configured to input an input signal provided by the signal input terminal to the control node. The control circuit is electrically connected with a working power supply terminal, and is configured to input an operation voltage provided by the working power supply terminal to the control node. The output circuit is electrically connected with a signal output terminal of the shift register and a clock signal line, and is configured to input one of a voltage of the control node and the first clock signal provided by the clock signal line to the signal output terminal.

The present disclosure provides a shift register unit. The shift register unit includes a pre-charge reset module; a pull-up module; a pull-down module; a first pull-down control module; and a second pull-down control module. The pre-charge reset module is connected to a forward scanning control signal input terminal, a reverse scanning control signal input terminal, a first signal input terminal, a second signal input terminal, and a pull-up control node. The pull-up module is connected to the pull-up control node, an input terminal of a first clock signal, and a signal output terminal. The first pull-down control module is connected to a pull-down control node, the forward scanning control signal input terminal, the reverse scanning control signal input terminal, the first signal input terminal, and the second signal input terminal.

A shift register circuit includes shift registers and each including: a first through fourth switches: in the first switch: a control end electrically coupled to a first node, a first end electrically coupled to a frequency signal, and a second end electrically coupled to an output pulse signal; in the second switch: a control end electrically coupled to the first node, a first end of electrically coupled to the frequency signal, and a second end electrically coupled to a control signal; in the third switch: a control end electrically coupled to a control signal, a first end electrically coupled to a first direct-current signal, and a second end electrically coupled to the first node; in the fourth switch: a control end electrically coupled to the control signal, a first end electrically coupled to a second direct-current signal, and a second end electrically coupled to the first node.

The present invention provides a shift register and a method for driving the same, a gate driving circuit and a display device, and belongs to the field of display technology. The shift register of the present invention includes an input module, an output pulling-up module and a reset-and-noise-reducing module, wherein the input module is connected to a signal input terminal, a second clock signal input terminal, a power supply voltage terminal and a pulling-up node, the output pulling-up module is connected to a first clock signal input terminal, the pulling-up node and a signal output terminal, and the reset-and-noise-reducing module is connected to the second clock signal input terminal, a reset signal input terminal, a low voltage terminal, the pulling-up node and the signal output terminal. The shift register of the present invention has a simple structure, thereby facilitating the implementation of a narrow-bezel display device.

A shift register circuit includes a plurality of shift registers. Each shift register includes a driving module, a voltage pre-storing module, a pulling up module, a pulling down module and a pulling down control module. The voltage pre-storing module includes a reset unit, an electric power storage unit and an output unit. The driving module, the voltage pre-storing module and the reset unit are electrically connected to a first node. One end of the electric power storage unit is electrically connected to the first node, and the another end is configured to receive the touch start signal and the touch end signal. The output unit is electrically connected between the first node and the second node. The pulling up module and the pulling down module are electrically connected to the second node. The pulling down control module is electrically connected to the pulling down module.

The disclosure provides a shift register, a gate driving circuit, a display panel and a display apparatus. The shift register may comprise an inputting module, a resetting module, a pulling up module, a pulling down module for a first node, a pulling down module for a second node, an output controlling module and an output noise reducing module. The inputting module is used to pull up a potential of the first node. The resetting module is used to pull down the potential of the first node. The pulling up module is used to pull up the potential of the second node. The pulling down module for the first node is used to pull down the potential of the first node. The pulling down module for the second node is used to pull down the potential of the second node. The output controlling module is used to control the scanning signal outputting terminal to output a signal from the second clock signal terminal; and to connect the low level signal terminal with the third node, which can ensure that the shift register can output a scanning signal in a corresponding period. Meanwhile, the signal from the third node is noise reduced by the output noise reducing module and then outputted to the scanning signal outputting terminal, which can reduce the noise of the signal outputted from the scanning signal outputting terminal.

A shift register and a display device are provided. The shift register includes a pre-charge unit, a pull-up unit, a first pull-down unit and a second pull-down unit. The pre-charge unit receives first and second input signals, and outputs a pre-charge signal via a first node. The pull-up unit receives the pre-charge signal and a clock signal, and outputs a scanning signal via a second node. The first pull-down unit receives the pre-charge signal, first and second pull-down control signals, and controls whether to pull-down the scanning signal to a reference voltage level. The second pull-down unit receives the pre-charge signal and first and second pull-down control signals, and controls whether to keep the scanning signal at the reference voltage level. The period of the first second pull-down control signal and the period of the second pull-down control signal are in a range from 12 frames to 180 frames.

Embodiments of the present disclosure provide a pulse generation device, an array substrate, a drive circuit and a driving method. The pulse generation device includes: a reset module making a pulse output end output low level, in response to a low level of a first input end or in response to a low level of a second input end and a low level of a third input end; a pulse generation module making the pulse output end output a high level, in response to a high level of the first input end, a high level of the second input end and a low level of the third input end or in response to a high level of the first input end, a low level of the second input end and a high level of the third input end.