The present disclosure relates to the field of display, and discloses a shifting register, a driving method, a gate driving circuit and a display device. The shifting register includes: an input sub-circuit, coupled to a signal input terminal, a first clock signal terminal and a first node; a control sub-circuit, coupled to the first clock signal terminal, a second clock signal terminal, the signal input terminal, a first power terminal, a second power terminal and a second node, where the first power terminal or the second power terminal determines a potential of the second node under the control of the first clock signal terminal, the second clock signal terminal and the signal input terminal; and an output sub-circuit, coupled to the first power terminal, the second power terminal, the first node, the second node and a signal output terminal.

A display drive circuit includes first shift registers from a first shift register of a 1st-stage to a first shift register of an Nth-stage; first shift registers of first A stages are virtual shift registers which are at least configured to make that an inputted second signal of a same pixel circuit has a delay of a set time length t relative to the first signal; and first shift registers of last (N-A) stages are at least configured to provide pixel circuits with the second signal; where t=a+b+c+d;

[00001]$A=\frac{t}{t_0*X}.$

A particular drive time sequence is formed in the present disclosure, which improves the characteristics of the drive transistor, solve the display problem caused by the tailing problem of the output signal of the first shift register, and improve image display quality.

An array base plate includes a silicon substrate including multiple cascaded EOA units disposed at a peripheral area; the EOA units are electrically connected to a pixel driving unit; each EOA unit includes an input circuit transmitting a signal input by a light-emitting control signal input line to the EOA unit; a first control circuit transmitting a second power signal input by a second power signal line to a first node, and transmitting a first power signal input by a first power signal line to a second node; a second control circuit transmitting a second clock signal to a third node or transmitting the second power signal to the third node; a pull-up circuit transmitting the first power signal to a light-emitting control signal output line, and a pull-down circuit transmitting the second power signal to the light-emitting control signal output line.

Disclosed are a display substrate and a display apparatus, wherein the display substrate includes a display region and a non-display region which includes a rounded corner region; the display substrate includes a circuit structure layer including a pixel circuit and a control drive circuit; the circuit structure layer further includes a plurality of reset output lines and a plurality of reset transfer lines located in the non-display region and disposed on a side of the control drive circuit close to the display region, and an extension direction of the reset output line and an extension direction of the reset transfer line intersect; the reset transfer line is connected with the pixel circuit; an orthographic projection of at least one reset transfer line located in the rounded corner region on the base substrate is partially overlapped with orthographic projections of the plurality of reset output lines on the base substrate.

A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes a gate driving circuit including shift register units and clock signal lines including a first clock signal line, a second clock signal line providing a second clock signal, and a third clock signal line providing a third clock signal. An input circuit of a n-th stage shift register unit in the shift register units is connected with the first clock signal line, a first control circuit of the n-th stage shift register unit is connected with the first clock signal line, the second clock signal line, and the third clock signal line, a second control circuit of the n-th stage shift register unit is connected with the second clock signal line, and a phase of the second clock signal is opposite to a phase of the third clock signal.

Provided is a display panel. The display panel includes multiple scanning lines, a gate driver circuit, and a timing controller. The timing controller is configured to: receive multiple data enable signals, generate a gate control signal, and provide the gate control signal for the gate driver circuit. The gate control signal includes a start signal, a first clock signal and a second clock signal. The multiple data enable signals are only within the active cycle. The timing controller is configured to generate a rising edge and a falling edge of the start signal within a time interval formed by a rising edge and a falling edge of a first data enable signal in the N.sup.th frame cycle.

Disclosed is a shift register which prevents current leakage and degradation of an oxide transistor due to light to improve output stability, and a display device using the same. The shift register includes a plurality of stages, and each stage includes a transmission line unit including a plurality of clock lines to supply a plurality of clock signals and a plurality of power lines to supply a plurality of voltages, a transistor unit including a plurality of transistors, and a light-shielding layer overlapping at least one transistor of the transistor unit so as to block light.

A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of on/off of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/?m (1?10.sup.?18 A/?m) or less. Therefore, the drive capability of the semiconductor device can be improved.

A display apparatus includes: a display panel including a plurality of pixels respectively connected to a plurality of gate lines; a gate driving circuit including a plurality of driving stages configured to apply gate signals to the gate lines; a voltage generator configured to output a gate-on voltage through a voltage output terminal thereof; and a signal controller configured to sense a variation in current of the voltage output terminal to output a back bias control voltage corresponding to the sensed current variation, wherein each of the driving stages comprises a plurality of oxide thin film transistors and at least one of the oxide thin film transistors is a four-terminal transistor in which a threshold voltage thereof is controlled by the back bias control voltage.

A scan line to which a selection signal or a non-selection signal is input from its end, and a transistor in which a clock signal is input to a gate, the non-selection signal is input to a source, and a drain is connected to the scan line are provided. A signal input to the end of the scan line is switched from the selection signal to the non-selection signal at the same or substantially the same time as the transistor is turned on. The non-selection signal is input not only from one end but also from both ends of the scan line. This makes it possible to inhibit the potentials of portions in the scan line from being changed at different times.