A flexible display panel and a driving method thereof, and a display device are provided. The flexible display panel includes a pixel region and a gate driving circuit region located outside the pixel region. The flexible display panel further includes a curvature adjusting unit located on two sides of the pixel region, the curvature adjusting unit includes a plurality of isosceles trapezoid units which are sequentially connected with each other through lower surfaces thereof, each isosceles trapezoid unit includes an upper surface, the lower surface, and a third waist surface and a fourth waist surface oppositely arranged between the upper surface and the lower surface, and a length of the upper surface between the third waist surface and the fourth waist surface is less than a length of the lower surface between the third waist surface and the fourth waist surface. In the case that the display panel is bent and in a bent portion of the display panel, the third waist surface of the isosceles trapezoid unit attaches to the fourth waist surface of the isosceles trapezoid unit adjacent thereto, and the upper surface of the isosceles trapezoid unit is connected with the upper surface of the isosceles trapezoid unit adjacent thereto.

Examples of the present disclosure provide apparatuses and methods related to performing a sort operation in a memory. An example apparatus might include a a first group of memory cells coupled to a first sense line, a second group of memory cells coupled to a second sense line, and a controller configured to control sensing circuitry to sort a first element stored in the first group of memory cells and a second element stored in the second group of memory cells by performing an operation without transferring data via an input/output (I/O) line.

A shift register device including a plurality of shift registers is provided. The shift registers are coupled to each other in series, where an N.sup.th stage shift register includes a voltage setting circuit, at least two control signal generators, at least two backup control signal generators and an output stage circuit. The at least two control signal generators are coupled to a first control terminal and a second control terminal, and the at least two backup control signal generators respectively receive at least two backup bias voltages, and respectively generate the first control voltage and the second control voltage according to the at least two backup bias voltages.

A shift register, a gate driving circuit, a display panel and a driving method. The shift register includes: an input circuit, an output circuit, a pull-up-node pull-down circuit, a first control circuit, a second control circuit and an output pull-down circuit. The first control circuit is configured to write a fourth clock signal into a first pull-down node and write a first power voltage into a second pull-down node responsive to a first control signal, and to write the first power voltage into the first pull-down node responsive to a voltage of a pull-up node. The second control circuit is configured to write the fourth clock signal into the second pull-down node and write the first power voltage into the first pull-down node responsive to a second control signal, and to write the first power voltage into the second pull-down node responsive to the voltage of the pull-up node.

Each Shift registers includes fourth switches and a voltage regulator circuit: a first switch: a control end electrically coupled to an input pulse signal, a first end electrically coupled to the input pulse signal, and a second end electrically coupled to a first node; a second switch: a control end electrically coupled to a second node, a first end electrically coupled to the first node, and a second end electrically coupled to a preset low potential; a third switch: a control end electrically coupled to a third node, a first end electrically coupled to a frequency signal, and a second end electrically coupled to an output end; a fourth switch: a control end electrically coupled to the second node, a first end electrically coupled to the output end, and a second end electrically coupled to the preset low potential.

The present application discloses a shift, register circuit having a plurality of shift register units cascaded in series. The shift register circuit includes a first shift register unit and a second shift register unit. The first shift register unit includes a first pull-up node and a first output terminal and the second shift register unit includes a second pull-up node and a second output terminal. The shift register circuit includes a stabilizer circuit coupled to both the first shift register unit and the second shift register unit such that the first pull-up node is directly connected to the second pull-up node as a common pull-up node and configured to maintain a potential level of the common pull-up node stable during a stabilizing period when none of the first output terminal and the second output terminal output a turn-on signal.

A display device includes a display panel having a curved side or a polygonal side, the display panel including a plurality of pixels in a display region, a gate driver including a plurality of normal stages connected to each other for outputting gate signals to the pixels via a plurality of gate lines, and a plurality of dummy stages between some of the normal stages, and a data driver providing data signals to the pixels via a plurality of data lines.

A GOA circuit and an LCD are disclosed. The GOA circuit includes a pull-up control circuit, a control terminal receives a first control signal, a first connection terminal receives a stage transfer signal, and a second connection terminal outputs a second control signal; a pull-up circuit includes a first switching tube, wherein a control terminal is coupled to the second connection terminal of the pull-up control circuit, a first connection terminal receives a clock signal, and a second connection terminal outputs a driving signal. When the first control signal is at a first level, the pull-up control circuit is conductive and outputs the second control signal such that the first switching tube is conductive. After a falling edge of the clock signal, a time interval that the first control signal is at the first level is greater than a preset value. A wrong charging by slow falling time is prevented.

The embodiments of the present disclosure provide a shift register unit, a method for driving the shift register unit, a gate driving circuit and a display apparatus. The shift register unit comprises a first input module, a first output module, a first reset module, a first storage module and a second reset module. The first input module is configured to output a first pull-up signal to the first output module based on a first input signal. The first output module is configured to output an output signal based on the first pull-up signal and a first clock signal. The first storage module is configured to store the first pull-up signal. The first reset module is configured to reset the first storage module based on a first reset signal. The second reset module is configured to reset the output from the first output module based on a second reset signal. The second reset signal is set to be valid while the first pull-up signal and the first clock signal are valid and a duration in which the second reset signal is valid is shorter than a duration in which the first clock signal is valid.

The present disclosure relates to display technology, and provides an inverter, a gate driving circuit and a display apparatus, capable of solving the problem that it is difficult to apply Scan Power technology in the display apparatus since a power signal outputted from the inverter has a small current. The inverter comprises: a current amplification module configured to amplify a current of the output terminal of the inverter based on a signal at a first clock signal terminal, a signal at a second clock signal terminal, a signal at a third clock signal terminal, a signal at a fourth clock signal terminal, a signal at a first input signal terminal, and a signal at a second input signal terminal, and to control the output terminal of the inverter to output a high level signal; and a pull-down module configured to control the output terminal of the inverter to output a low level signal. The inverter according to the present disclosure may be applied in a display apparatus employing the Scan Power technology.