A memory device may include N memory areas that are divided into a first group and a second group, and are selected by area selection signals corresponding to the N memory areas among N area selection signals, N*M pipe latches that store output data of memory areas corresponding to the N*M pipe latches among the N memory areas, a first pipe output signal generation circuit that generates 1-1.sup.th to 1-M.sup.th pipe output signals of pipe latches, which correspond to memory areas belonging to the first group, in response to an area selection signal corresponding to a predetermined memory area of memory areas, and a second pipe output signal generation circuit that generates 2-1.sup.th to 2-M.sup.th pipe output signals of pipe latches, which correspond to memory areas belonging to the second group, in response to an area selection signal corresponding to a predetermined memory area of memory areas.

The present application discloses a gate driver on array (GOA) circuit including a first GOA circuit; a second GOA circuit; and a voltage transmitting circuit configured to transmit an output voltage from the first GOA circuit to the second GOA circuit as an input voltage for the second GOA circuit; the output voltage from the first GOA circuit and the input voltage for the second GOA circuit having a substantially the same voltage level. An input port of the voltage transmitting circuit is connected to an output port of the first GOA circuit and configured to receive the output voltage from the first GOA circuit; and an output port of the voltage transmitting circuit is connected to an input port of the second GOA circuit and configured to output a forwarded voltage to the second GOA circuit as the input voltage for the second GOA circuit.

A display circuit and a driving method thereof and a display apparatus are provided. The display circuit comprises a pixel unit (11), a first gate driving unit (12) and a second gate driving unit (13); wherein the first gate driving unit (12) is configured to input a first gate driving signal to the pixel unit (11); the second gate driving unit (13) is configured to input a second gate driving signal to the pixel unit (11); and the pixel unit (11) is configured to perform threshold compensating and gray scale displaying simultaneously under the control of the first gate driving signal and the second gate driving signal. The apparatus and method is capable of reducing the complexity in design of the display circuit, which is advantageous for raising density of pixels of the display panel. The apparatus and method are applicable to manufacture a display.

A shift register unit is provided. The shift register unit includes a first input module configured to output a first voltage signal as a pull-up control signal under the control of a first signal, a first reset module configured to reset the pull-up control signal under the control of a first reset signal, a pull-up module configured to output a first clock signal under the control of the pull-up control signal, a pull-down control module configured to output a second clock signal as a pull-down control signal under the control of a second clock signal, a pull-down module configured to pull down a voltage of the pull-up control signal, a first output module, and a second output module.

The CMOS GOA circuit of reducing clock signal loading comprises the input control module (1), the latch module (2), the reset module (3), the signal process module (4) and the output buffer module (5); in the input control module (1), the clock signal (CK(M)) merely needs to control the second N type thin film transistor and the fifth N type thin film transistor (T2, T5), and the amount of the thin film transistors driven by the clock signal can be decreased to reduce the clock signal loading, and to lower the RC delay and the power consumption of the clock signal; the latch module (2) utilizes the inverted scan drive signal (XGate(N2)) of the two former N-2th stage GOA unit to be the input control signal of the stage transfer signal Q(N) to solve the competition problem occurs as the stage transfer signal (Q(N)) is inputted.

Embodiments of the present disclosure provide a shift register unit, a gate driving circuit and driving method thereof, and a display apparatus. The shift register unit comprises a first controlling sub-circuit, a second controlling sub-circuit, a first pulling up sub-circuit, a second pulling up sub-circuit, a first pulling down sub-circuit and a second pulling down sub-circuit. The first controlling sub-circuit controls the potential at the first node. The voltage of a second clock signal terminal can be outputted to the first and the second outputting terminals by the first and the second pulling down sub-circuits, respectively. The first node, the first clock signal terminal and the second voltage terminal may control the potential at a second node through the second controlling sub-circuit. Under the control of the potential at the second node, the voltage of the second voltage terminal can be outputted to the first and the second outputting terminals.

A display device includes a display panel having a curved side or a polygonal side, the display panel including a plurality of pixels in a display region, a gate driver including a plurality of normal stages connected to each other for outputting gate signals to the pixels via a plurality of gate lines, and a plurality of dummy stages between some of the normal stages, and a data driver providing data signals to the pixels via a plurality of data lines.

A shift register and a driving method therefor, a gate driving circuit and a display apparatus. The shift register comprises a trigger reset module, a pull-up module, a first capacitor and a pull-down module, and further comprises a denoising module. The pull-up module is used for pulling up a signal output from an output terminal of the shift register and a signal output from a transmission signal output terminal. The pull-down module is used for pulling down a signal output from the output terminal of the shift register and the signal output from the transmission signal output terminal. The denoising module is used for cutting off the connection path between the transmission signal output terminal and a second terminal of the first capacitor in a pull-down phase. The shift register, by providing the denoising module, makes it possible to prevent a coupling effect of the capacitor from making a transmission signal output from the transmission signal output terminal generate a sparkle noise or the like, when a voltage jump occurs at a pull-up node thereof, so that a shift transmission signal of the shift register is more stable, thereby making the signal output from the shift register more stable.

The present disclosure discloses a shift register unit and a driving method thereof, a shift register circuit and a display device, and relates to the field of display technology, in order to solve problems of the conventional shift register that it has a complex structure, and occupies a too larger space. The shift register unit comprises an input module for receiving a signal of an input signal terminal and a signal of a high level terminal, a reset module for resetting an output terminal of the shift register unit and a pull-up control node, a pull-down module for discharging the pull-up control node and the output terminal of the shift register unit, a pull-down control module for generating a power supply enable signal and a power supply signal, and an output control module for generating a gate drive signal and outputting the power supply enable signal, the power supply signal and the gate drive signal. The shift register unit provided by the present disclosure is applied to the display device.

Embodiments of the present invention provide a gate driver circuit, a touch display device and a touch display driving method. The gate driver circuit includes a plurality of GOA unit groups arranged successively and control units arranged between every two adjacent GOA unit groups, each of the GOA unit groups comprising a plurality of shift registers which are cascaded. The control unit is configured to output a start control signal at a high level to a signal input end of a first stage shift register of a next GOA unit group corresponding thereto, after a last stage shift register of a previous GOA unit group corresponding thereto completes driving for a corresponding gate line and a predetermined time elapses, so as to pre-charge the first stage shift register of the next GOA unit group.