Provided are a display panel and a display device. The display panel includes a drive circuit including cascaded N stage shift registers. A shift register includes a control unit, an initial output unit and a first output unit. The control unit is configured to at least receive an input signal and control a signal of the first output node and a signal of the second output node. The initial output unit is configured to at least receive a signal of the first output node and a signal of the second output node, and control an initial output signal; the initial output signal of an x.sup.th stage shift register is the input signal of a y.sup.th stage shift register. The first output unit is configured to at least receive the signal of the first output node and the signal of the second output node, and control a first output signal.

A scan line to which a selection signal or a non-selection signal is input from its end, and a transistor in which a clock signal is input to a gate, the non-selection signal input to a source, and a drain is connected to the scan line are provided. A signal input to the end of the scan line is switched from the selection signal to the non-selection signal at the same or substantially the same time as the transistor is turned on. The non-selection signal is input not only from one end but also from both ends of the scan line. This makes it possible to inhibit the potentials of portions in the scan line from being changed at different times.

An electronic display includes an active area including multiple pixels. The electronic display also includes a first row driver set including a first column of row drivers and a second column of row drivers. A first active row driver in the first column of row drivers drives a first portion of the multiple pixels, and a first spare row driver in the second column of row drivers is in an inactive state. The electronic display also includes a second row driver set including a third column of row drivers and a fourth column of row drivers. A third active row driver in the third column of row drivers drives a second portion of the multiple pixels, and a second spare row driver in the fourth column of row drivers is inactive.

A display substrate includes a base substrate including a display area and a peripheral area on at least one side of the display area; a pixel array, located in the display area and including multiple pixel units; and, a scan driving module, located in a driving circuit area of the peripheral area, and including multiple shift register units, multiple signal lines being arranged in one shift register units, and extending along a first direction; wherein a ratio of a sum W1 of widths of the multiple signal lines in a second direction to a width W2 of the shift register unit in the second direction is W1/W2, and a length of at least one pixel unit along the first direction is a pixel pitch value; the first direction intersects the second direction; a product of W1/W2 and the pixel pitch value is greater than 18 um and less than 40 um.

A shift register includes a first scan unit including a first input circuit and a first output circuit, and a second scan unit including a second input circuit, a second output circuit, and a fourth transistor. The first input circuit is electrically connected to an input signal terminal and a first pull-up node. The first output circuit is electrically connected to the first pull-up node, a first clock signal terminal, a second clock signal terminal, a shift signal terminal, and a first scan signal terminal. The second input circuit is electrically connected to the input signal terminal and a second pull-up node. The second output circuit is electrically connected to the second pull-up node, a third clock signal terminal, and a second scan signal terminal. The fourth transistor is electrically connected to the second pull-up node, a sub-clock signal terminal, and a dummy shift signal terminal.

A display device includes a display panel, a gate driving circuit, and an image determination unit. The gate driving circuit includes a double gate transistor. The image determination unit outputs an image determination signal to a second control electrode of the double gate transistor. When the display panel displays a still image, the double gate transistor is turned on by the image determination signal so that each of gate signals outputted from stages connected in cascade to a stage including the double gate transistor among stages included in the gate driving circuit has a gate-off voltage.

A shift register unit and a method of driving the same, a gate driving circuit and a display device are provided. The first pull-up circuit of the shift register is configured to output a signal of the first clock signal end to the first signal output end under a control of the pull-up node. The second pull-up circuit is configured to output the signal of the first clock signal end to the second signal output end under a control of the pull-up node. The first pull-down circuit is configured to pull down a potential of the pull-up node and a potential of the first signal output end to the potential of the second voltage end under a control of the pull-down node. The second pull-down circuit is configured to pull down a potential of the second signal output end to the potential of the second voltage end under a control of the pull-down node.

A display panel includes a shift register and an active terminator. The shift register has a drive circuit coupled to one end of a gate line. The active terminator is coupled to the other end of the gate line and includes a first transistor, a second transistor, and a first capacitor. The first transistor has a first terminal connected to a first clock signal, a second terminal connected to the gate line, and a third terminal. The second transistor has a first terminal connected to a first internal node, a second terminal connected to the third terminal of the first transistor, and a third terminal connected to a first DC voltage source. The first capacitor has a first terminal connected to the gate line and a second terminal connected to the third terminal of the first transistor and the second terminal of second transistor.

The present disclosure provides a gate driving circuit, a method for detecting the gate driving circuit, an array substrate and a display apparatus. The gate driving circuit comprises a plurality of cascaded gate driving units, access units, a first signal line and a second signal line. Each access unit is connected to its corresponding gate driving unit and the gate driving unit at the next stage to its corresponding gate driving unit. The access unit corresponding to the gate driving unit at each odd stage is connected to the first signal line such that the first signal line detects an output signal from that gate driving unit via the access unit, and the access unit corresponding to the gate driving unit at each even stage is connected to the second signal line such that the second signal line detects an output signal from that gate driving unit via the access unit.

There provide an emission electrode scanning circuit, an array substrate and a display apparatus. The emission electrode scanning circuit includes a plurality of sub scanning circuits connected in cascades, each of which includes a shift register unit, a scanning signal generation unit and a driving output unit. Each sub scanning circuit provides a driving signal to the emission electrode respectively, thereby avoiding bringing in a plurality of driving signal lines from outside of the array substrate. And the plurality of sub scanning circuits shares the emission electrode driving signal line and needs an input of only one start signal to drive the emission electrode scanning circuit to send the emission electrode driving signal progressively. The emission electrode scanning circuit is suitable to be integrated in the seal region of the array substrate, without setting the Fan-out having numerous input lines, which is advantageous for implementing the narrow frame of the display apparatus and also avoids crosstalk produced between the input lines and the gate voltage lines.