A gate drive circuit and a display panel. The gate drive circuit includes one or more shift register groups. Each of the shift register groups includes N shift adjacent registers that output in sequence, with N being an integer greater than or equal to 3. Each of the shift registers includes a first output stage and a frequency division control module. The first output stage is configured to output a gate drive signal. The frequency division control module is configured to control outputting of the gate drive signal based on a refresh frequency. A control end of each frequency division control module in each of the shift register groups receives a control signal with a different phase and a same frequency, respectively, to adjust a pulse width of the gate drive signal and maintain a same pulse width at different refresh frequencies.

A first flipflop outputs a first signal synchronized with a first clock signal. In the first transistor, the first clock signal is input to a first terminal and the second signal is output from a second terminal. In the fourth transistor, a first signal is input to a first terminal and a second terminal is electrically connected to a gate of the first transistor. In the sixth transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the fourth transistor, and the gate of the sixth transistor is electrically connected to the first terminal.

Provided is a gate driver circuit. The gate driver circuit is applicable to a display panel, wherein the display panel includes a plurality of rows of pixels; the gate driver circuit including at least one gate driver sub-circuit; wherein the gate driver sub-circuit includes: at least two shift register groups, wherein each shift register group includes a plurality of shift register units; at least two first dummy units, wherein the at least two first dummy units are respectively coupled to a same input enable terminal and the at least two shift register groups; and at least two second dummy units, wherein the at least two second dummy units are coupled to the at least two shift register groups.

A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of on/off of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/m (110.sup.18 A/m) or less. Therefore, the drive capability of the semiconductor device can be improved.

A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings.

A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes a gate driving circuit including shift register units and clock signal lines including a first clock signal line, a second clock signal line providing a second clock signal, and a third clock signal line providing a third clock signal. An input circuit of a n-th stage shift register unit in the shift register units is connected with the first clock signal line, a first control circuit of the n-th stage shift register unit is connected with the first clock signal line, the second clock signal line, and the third clock signal line, a second control circuit of the n-th stage shift register unit is connected with the second clock signal line, and a phase of the second clock signal is opposite to a phase of the third clock signal.

A display panel and a display device. The display panel comprises: a substrate, a display area (100) provided with at least one light-emitting signal line (E), at least one first reset signal line (R) and sub-pixels arranged in an array, at least one sub-pixel (P1, P2, P3) comprising: a light-emitting device (L) and a pixel circuit. The first reset signal line (R) is configured to provide a reset control signal for the pixel circuit, the light-emitting signal line is configured to provide a light-emitting control signal for the pixel circuit to provide a driving current. For the first reset signal line and the light-emitting signal line E connected to a same pixel circuit, the duration in which the signal of the light-emitting signal line is an invalid level signal is equal to the duration in which the signal of the first reset signal line is a valid level signal.

A scan circuit is provided. The scan circuit includes a plurality of stages. A respective stage of the scan circuit includes a respective scan unit configured to provide a control signal to one or more rows of subpixels. A respective scan unit includes a first subcircuit, a second subcircuit, a third subcircuit, a fourth subcircuit. A pull-up node is coupled to the second subcircuit, the third subcircuit, and the fourth subcircuit. A pull-down node is coupled to the second subcircuit, the third subcircuit. The denoising subcircuit is coupled to a pull-up node and the input terminal, or coupled between a third power supply voltage terminal and the pull-down control node.

A display device includes a substrate having a display region in which a plurality of pixels are arrayed in a first direction and a second direction different from the first direction, a plurality of scanning lines coupled to the pixels arrayed in the first direction, a plurality of signal lines coupled to the pixels arrayed in the second direction, a gate driver configured to supply a scanning signal to the scanning lines, and a signal line selection circuit configured to supply a pixel signal to the signal lines.

Provided is a shift register unit. The shift register unit includes: a first input circuit, coupled to a first clock terminal, an input terminal, a first node and a second node; a second input circuit, coupled to the first node, the first clock terminal, a first power terminal and a third node; a first control circuit, coupled to the input terminal, the first clock terminal, the second node, a second power terminal, a second clock terminal and the third node; a second control circuit, coupled to the third node, the second clock terminal, the first node, the first power terminal, the second power terminal, a fourth node and a fifth node; and an output circuit, coupled to the fourth node, the fifth node, the first power terminal, the second power terminal and an output terminal.