A shift register unit is provided. The shift register unit includes a precharging module, a resetting module, a pull-up control module and a noise reduction module. The precharging module is connected to the resetting module and a pull-up node, the resetting module is connected to the pull-up node, the noise reduction module and an output end, the pull-up control module is connected to the pull-up node, the noise reduction module and the output end, and the noise output module is connected to the output end.

A shift register unit and a control method thereof, a gate driving circuit, and a display device. The shift register unit includes a signal input module, connected to a signal input terminal, a first clock signal terminal and a control node; a pull-down module, connected to the control node, a first voltage terminal and a signal output terminal; a first pull-up control module, connected to the control node, the pull-up module and a second voltage terminal; a second pull-up control module, connected to the control node, the pull-up module, the first clock signal terminal, the first voltage terminal and a second clock signal terminal; and a pull-up module, connected to the signal output terminal and the second voltage terminal. The problem that it is difficult to realize a narrow display frame by the bonding process due to size increase of the driving circuit can be solved.

A display device includes a first substrate and a second substrate opposite to each other, a gate line on the first substrate, a gate driver which is connected to the gate line, a clock line which transmits a clock signal, a connecting line which connects the clock line and the gate driver, a common electrode on the second substrate, the common electrode overlapping the clock line and the connecting line, and a compensation pattern which overlaps the common electrode and extends from the connecting line.

A gate driving circuit, an array substrate, and a display device are disclosed. The present disclosure relates to the technical field of display, and the technical problem of poor quality of the waveform of the gate driving signal that is output by the traditional circuit manufactured through GOA technology can be solved. The gate driving circuit is used for outputting the gate driving signal to G.sub.n and comprises a pull-up circuit, a download transistor, and a pull-down circuit. The pull-up circuit is used for outputting a high-level signal to a reference point of said gate driving circuit, a first input end of said pull-up circuit is connected with G.sub.n1, a second input end thereof is connected with G.sub.n2, and an output end thereof is connected with said reference point.

An asynchronous first in first out memory device eliminates the need for synchronizers. The device includes pipeline of data registers. The data registers include a first register to accept data writes of data and a last register data reads. Each register has an enable input to indicate a full condition allowing a read and an empty condition allowing a write. A bubble inserter circuit inserts a bubble in the first register to prevent a completely empty condition for all registers. Controllers are associated with each register to allow the bubble or written data to be passed from the first register to the last register. A near empty detect circuit is coupled to the registers to determine a nearly empty condition of the pipeline. An arbiter determines whether a data write proceeds or a bubble insertion proceeds for the first register when the plurality of registers is near empty.

The present disclosure relates to the field of display technologies, and specifically to a shift register unit, a gate driving circuit comprising the shift register unit and a display device comprising the gate driving circuit. In accordance with an aspect of the present disclosure, a shift register unit is provided, which comprises a set module, a pull-down module, a pull-down control module, a reset module and an output module, wherein the pull-down module is only configured with two transistors to provide discharge channels via the first node and the output terminal, respectively.

According to the embodiments of the disclosure, a shift register and a method for driving the same, a gate driving circuit and a display apparatus may be provided. The shift register includes an input module, a node control module, a first output module and a second output module. The input module may control a potential at a first node via an input signal end and a first clock signal end, the node control module may configured to control the potential at a first node via a first control signal end and a DC signal end, the first output module may control the potential at a driving signal output end via a second control signal end and the DC signal end, and the second output module may maintain a voltage difference between the first node and the driving signal output end in a stable state when the first node is in a floating state and control the potential at the driving signal output end via the first node and the second clock signal end. By cooperating with each other, these four modules may achieve the outputs of scanning signals with a simpler structure and a fewer signal lines, so as to simplify the manufacturing process and reduce the production cost.

A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

A gate drive integrated circuit (IC) for a display device includes a start pulse modulator configured to receive a start pulse or a front-end carry pulse alternating between a first logic level and a second logic level to output a modulation start pulse or a modulation carry pulse that is generated by modulating a logic level shift time of the start pulse or the front-end carry pulse; and a shift register configured to receive and sequentially output the modulation start pulse or the modulation carry pulse. The start pulse modulator is further configured to output the modulation start pulse or the modulation carry pulse having the second logic level at a time when a logic level of the start pulse or the front-end carry pulse has a third logic level between the first logic level and the second logic level.

A disclosed display device comprises a display panel having a display area configured to display an image. The display panel includes in the display area a plurality of data lines extending in a first direction, a plurality of gate lines extending in a second direction and crossing the data lines, and a plurality of pixels defined by the data lines and the gate lines, and arranged in a plurality of rows and a plurality of columns. The display device further comprises at least one gate in panel (GIP) circuit disposed in the display area and having a plurality of signal lines and a plurality of transistors each respectively disposed between two adjacent columns of the pixels among the columns.