Provided is a charging scan and charge sharing scan double output GOA circuit to combine the time sequence and circuit. The nth stage GOA unit circuit receives the first, the second low frequency clock signals (LC1, LC2), the direct current low voltage signal (Vss), the Mth, M−2th high frequency clock signals (CK(M), CK(M−2)), a stage transfer signal (ST(n−2)) generated by the n−2th stage GOA unit circuit, a charging scan signal (CG(n−2)) generated by the n−2th stage GOA unit circuit and a stage transfer signal (ST(n+2)) generated by the n+2th stage GOA unit circuit, the charging scan signal (CG(n)), a charge sharing scan signal (SG(n−2)) generated by the n−2th stage GOA unit circuit and the stage transfer signal (ST(n)) are respectively outputted with different TFTs; the nth stage GOA unit circuit comprises a transmission module (100), a transfer regulation module (200), an output module (300), a rapid pull-down module (400) and a pull-down holding module (500).

A shift register unit, a gate driving circuit, a display device and a driving method. The shift register unit includes a blank input circuit, a blank pull-up circuit, a display input circuit, and an output circuit. The blank input circuit charges and holds the level of the pull-up control node, the blank pull-up circuit uses a first clock signal to charge a pull-up node, the display input circuit charges the pull-up node, and the output circuit outputs a plurality of output clock signals respectively to a plurality of output terminals. The plurality of output terminals include a shift signal output terminal and a plurality of pixel signal output terminals. The plurality of pixel signal output terminals are configured to respectively output a plurality of pixel signals to a plurality of rows of pixel units.

The present invention provides a Gate driver on Array circuit, a display panel and a display device. The Gate driver on Array circuit comprises: shift register SR circuits of multiple stages and a signal connection circuit of the shift register SR circuits of multiple stages, and the shift register SR circuit of each stage comprises: a pre-charge controller, three thin film transistors and a capacitor; and the SR circuit of each stage further comprises: at least one switch, and a G electrode of the switch is inputted with a touch panel scan signal, and a S electrode of the switch is coupled to a K output end, and a D electrode of the switch is coupled to a scan line gate electrode signal of the SR circuit; the K output end inputs a K signal, and the K signal is synchronized with a touch panel signal TP signal.

A shift register includes an output sub-circuit and a coupling sub-circuit. The output sub-circuit is coupled to a second clock signal terminal, a pull-up node and a signal output terminal. The output sub-circuit is configured to output a second clock signal received at the second clock signal terminal to the signal output terminal under a control of a voltage of the pull-up node. The coupling sub-circuit is coupled to the second clock signal terminal and a pull-down node. The coupling sub-circuit is configured to couple a voltage of the pull-down node through the second clock signal received at the second clock signal terminal.

The present invention provides a data acquiring module, comprising: a data input and output terminal, through which data enter into the data acquiring module, and which can output data independently; a shift register groups, each of which comprises (b−1) serially connected shift registers, and an output terminal of each shift register being able to output data independently, wherein a and b are integers greater than 1; and (a−1) serially connected first-in first-out memories connected to (a−1) shift register groups respectively, and the output terminal of each first-in first-out memory being able to output data independently, an input terminal of the last shift register in the shift register group without a corresponding first-in first-out memory in the a shift register groups, and the input terminal of the last first-in first-out memory of the serially connected first-in first-out memories being connected to the data input and output terminal. The present invention also provides a data processing unit, a driver and a display device.

A gate driving circuit includes a plurality of shift registers coupled in series. An nth shift register includes a driving circuit and a pull-down circuit. The driving circuit is electrically coupled to an output node and a first node. The driving circuit is configured to receive a first clock signal and output a gate signal according to the first clock signal. The pull-down circuit is electrically coupled to the output node. The pull-down circuit is configured to receive an (n−m)th gate signal and an (n+m)th gate signal, and pull-down the gate signal to a low voltage level according to one of the (n−m)th gate signal and the (n+m)th gate signal, wherein m and n are positive integers.

Provided are a display panel and display device. The display panel includes a driver circuit, where the driver circuit includes an N-stage cascaded shift register which includes a first control unit, a second control unit, a third control unit, and a fourth control unit. The first control unit is configured to receive an input signal and control a signal of a first node in response to a first clock signal. The second control unit is configured to control a signal of a second node. The third control unit is configured to receive the first voltage signal and generate an output signal in response to a signal of a third node, or receive the second voltage signal and generate an output signal in response to the signal of the second node. The fourth control unit is connected to the third node.

A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of on/off of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/μm (1×10.sup.−18 A/μm) or less. Therefore, the drive capability of the semiconductor device can be improved.

The embodiments of the present disclosure propose a shift register, a driving method thereof, a gate driving circuit and a display apparatus. The shift register comprises an input sub-circuit coupled to an input terminal and a pull-up node, and configured to charge the pull-up node under control of an input signal from the input terminal; an output sub-circuit coupled to a clock signal terminal, the pull-up node, and an output terminal, and configured to transmit a clock signal from the clock signal terminal to the output terminal under control of the pull-up node; and an output shaping sub-circuit coupled to the clock signal terminal, the output terminal, and a first voltage signal terminal, and configured to transmit a first voltage signal from the first voltage signal terminal to the output terminal under control of the clock signal.

A shift register, a gate driving circuit and a display apparatus are provided. The shift register comprises a pull-up node control unit, a pull-down node control unit, a pull-up output unit, a noise reduction unit, and a touch scanning control unit. Herein, the pull-up node control unit is connected to a first input terminal, a second input terminal, a first power supply terminal, a second power supply terminal, and a pull-up node (PU); the pull-down node control unit is connected to a high level terminal (VGH), a low level terminal (VGL) and the pull-up node (PU) and a pull-down node (PD); the pull-up output unit is connected to a clock signal input terminal (CLK), the pull-up node (PU), a signal output terminal (Output); the noise reduction unit is connected to the pull-up node (PD) and the low level terminal (VGL); the touch scanning control unit is connected to a control signal input terminal (SW), the pull-up node (PU), the signal output terminal (Output), and the low level terminal (VGL).