The present invention discloses a liquid crystal display device and a GOA scanning circuit. The GOA scanning circuit includes multiple cascaded GOA circuit units, and an n-th stage GOA circuit unit includes: a forward and backward scanning module including a first thin-film transistor and a second thin-film transistor, wherein, two current path terminals of the first thin-film transistor are respectively connected with a first clock signal and a first node; two current path terminals of the second thin-film transistor are respectively connected with a second clock signal and the first node; a control terminal of the first thin-film transistor is connected with a stage-transferring signal STn1 of a previous stage GOA circuit unit; a control terminal of the second thin-film transistor is connected with a stage-transferring signal STn+1 of a next stage GOA circuit unit.

A gate driving circuit including a plurality of stages to respectively output gate signals to gate lines and connected to each other in cascade, an ith stage from among the plurality of stages including: a first output unit to generate a gate signal from a clock signal received at an input terminal; a first control unit to control the potential of a first node; a first pull-down unit to provide a first low voltage to a gate output terminal to drop down the gate signal, the first low voltage being lower than a gate off voltage of the gate signal; a first holding unit and a stabilization unit, each to provide a second low voltage having a higher level than that of the first low voltage to the gate output terminal; and a second control unit to control an operation of the first holding unit.

The present disclosure provides a shift register, a gate driving circuit and a display device. The shift register comprises a set/reset unit, a pull down control unit, a pull down unit and an output unit. The set/reset unit sets or resets a pull up node in the output unit in response to a set signal or a reset signal. The output unit outputs an output signal in response to a first control signal through an output terminal of the shift register. The pull down control unit sets a pull down node in the pull down unit in response to a second control signal. The pull down control unit comprises a transistor and a capacitor, and the second control signal is applied to a gate of the transistor through the capacitor.

A shift register, a driving circuit, a driving method and a display device are provided. The shift register includes: an input circuit configured to provide a first voltage or a second voltage to a first node and a light-emitting control signal terminal under a control of a first input signal and a second input signal; a processing circuit configured to provide the first voltage or the second voltage to a second node under a control of the first input signal and a potential of the first node; and an output circuit configured to provide the first voltage or the second voltage to a first output scanning signal terminal under control of a first clock signal and the potential of the first node, and provide the first voltage or the second voltage to a second output scanning signal terminal under a control of a potential of the first output scanning signal terminal.

The present disclosure provides a gate driving circuit, a method of driving a gate driving circuit, and a display panel. The gate driving circuit includes a plurality of driving units connected in cascade. Each driving unit includes: N shift register units; and a mode control circuit connected to the N shift register units, wherein the mode control circuit is configured to receive a control signal for the driving unit, and connect the N shift register units in one of a plurality of resolution modes under the control of the control signal.

Provided is a gate driver circuit. The gate driver circuit is applicable to a display panel, wherein the display panel includes a plurality of rows of pixels; the gate driver circuit including at least one gate driver sub-circuit; wherein the gate driver sub-circuit includes: at least two shift register groups, wherein each shift register group includes a plurality of shift register units; at least two first dummy units, wherein the at least two first dummy units are respectively coupled to a same input enable terminal and the at least two shift register groups; and at least two second dummy units, wherein the at least two second dummy units are coupled to the at least two shift register groups.

A display substrate, includes: a display region. The display region includes a plurality of sub-pixels disposed on a substrate, a plurality of first signal lines extending in a first direction, and a plurality of data lines extending in a second direction. At least one sub-pixel includes a driving circuit, and the driving circuit includes a plurality of transistors and at least one storage capacitor. The transistor at least includes a first conductive layer and a second conductive layer. The plurality of first signal lines is located in a third conductive layer. The third conductive layer is located on a side of a control electrode of a transistor of the driving circuit away from the substrate.

A display substrate and a display apparatus. The display substrate includes a display area provided with pixel circuits arranged in an array and a non-display area provided with M light emitting driving circuits, M control driving circuits and M reset driving circuits. Odd-numbered light emitting driving circuits are electrically connected with first and second light emitting clock signal lines, and even-numbered light emitting driving circuits are connected with third and fourth light emitting clock signal lines; and/or, odd-numbered control driving circuits are electrically connected with first and second control clock signal lines, and even-numbered control driving circuits are connected with third and fourth control clock signal lines; and/or, odd-numbered reset driving circuits are electrically connected with first and second reset clock signal lines, and even-numbered reset driving circuits are connected with third and fourth reset clock signal lines.

A gate drive circuit and a display panel. The gate drive circuit includes one or more shift register groups. Each of the shift register groups includes N shift adjacent registers that output in sequence, with N being an integer greater than or equal to 3. Each of the shift registers includes a first output stage and a frequency division control module. The first output stage is configured to output a gate drive signal. The frequency division control module is configured to control outputting of the gate drive signal based on a refresh frequency. A control end of each frequency division control module in each of the shift register groups receives a control signal with a different phase and a same frequency, respectively, to adjust a pulse width of the gate drive signal and maintain a same pulse width at different refresh frequencies.

In disclosed circuit arrangements, memory cell arrays are addressed by a first portion of an input address, and memory cells within each memory cell array are addressed by a second portion of the input address. A first first-in-first-out (FIFO) buffer is coupled to the memory cell arrays and delays the second portion of each input address to the memory cell arrays for a sleep period. Control circuits respectively coupled to the memory cell arrays include second FIFO buffers and decode the first portion of each input address and generate corresponding states of enable signals. The control circuits store the corresponding states of the enable signals in the second FIFO buffers concurrently with input of the second portion of each input address to the first FIFO buffer. The second FIFO buffers delay output of the corresponding states of the enable signals to the memory cell arrays for the sleep period. Each control circuit further switches a corresponding memory cell array into a sleep mode in response to all states of the enable signal in the corresponding second FIFO buffer being in a non-enabled state.