A shift register and a driving method therefor, a gate driving circuit and a display apparatus. The shift register comprises a trigger reset module, a pull-up module, a first capacitor and a pull-down module, and further comprises a denoising module. The pull-up module is used for pulling up a signal output from an output terminal of the shift register and a signal output from a transmission signal output terminal. The pull-down module is used for pulling down a signal output from the output terminal of the shift register and the signal output from the transmission signal output terminal. The denoising module is used for cutting off the connection path between the transmission signal output terminal and a second terminal of the first capacitor in a pull-down phase. The shift register, by providing the denoising module, makes it possible to prevent a coupling effect of the capacitor from making a transmission signal output from the transmission signal output terminal generate a sparkle noise or the like, when a voltage jump occurs at a pull-up node thereof, so that a shift transmission signal of the shift register is more stable, thereby making the signal output from the shift register more stable.

A display device includes a display panel, a gate driving circuit, and an image determination unit. The gate driving circuit includes a double gate transistor. The image determination unit outputs an image determination signal to a second control electrode of the double gate transistor. When the display panel displays a still image, the double gate transistor is turned on by the image determination signal so that each of gate signals outputted from stages connected in cascade to a stage including the double gate transistor among stages included in the gate driving circuit has a gate-off voltage.

The present invention provides a multi-phase clock generating circuit and liquid crystal display panel, said circuit comprising: a shift register including N shift registration units, which are cascaded with each other; a first output terminal of nth shift registration units connected to a first input terminal of an (n+1)th shift registration unit; a thin film transistor set including N thin film transistors, said control terminals of said thin film transistors of a nth stage are respectively connected to said first output terminals of (Nn+1) shift registration units.

The present disclosure provides a shift register unit including a pull-up module, an input module, a pull-down control module, a pull-down module, a reset discharging module, a voltage dividing module, a holding module, and a far end pull-down module. The shift register unit is designed in a split manner in order to perform pull-down compensation to the output signal at the far end, saving the low voltage signal at the far end, thereby saving the space and facilitating the design. The present disclosure further provides a gate driving device and a display device using the shift register unit.

A shift register circuit includes a plurality of shift registers. Each shift register includes a driving module, a voltage pre-storing module, a pulling up module, a pulling down module and a pulling down control module. The voltage pre-storing module includes a reset unit, an electric power storage unit and an output unit. The driving module, the voltage pre-storing module and the reset unit are electrically connected to a first node. One end of the electric power storage unit is electrically connected to the first node, and the another end is configured to receive the touch start signal and the touch end signal. The output unit is electrically connected between the first node and the second node. The pulling up module and the pulling down module are electrically connected to the second node. The pulling down control module is electrically connected to the pulling down module.

Embodiments of the present invention provide a gate driver circuit, a touch display device and a touch display driving method. The gate driver circuit includes a plurality of GOA unit groups arranged successively and control units arranged between every two adjacent GOA unit groups, each of the GOA unit groups comprising a plurality of shift registers which are cascaded. The control unit is configured to output a start control signal at a high level to a signal input end of a first stage shift register of a next GOA unit group corresponding thereto, after a last stage shift register of a previous GOA unit group corresponding thereto completes driving for a corresponding gate line and a predetermined time elapses, so as to pre-charge the first stage shift register of the next GOA unit group.

Provided are a gate driving circuit and a display device using the same. The gate driving circuit includes: a plurality of stages, each stage sequentially receiving a phase-delayed clock and sequentially generating an output. An nth stage (n is a positive integer) includes: a first inverter including a first PMOS transistor and a first NMOS transistor; a second inverter including a second PMOS transistor and a second NMOS transistor; and a reset signal line connected to a source terminal of the second NMOS transistor and supplying a reset signal to initiate the nth stage.

A signal comprising a first edge and a second edge is received. The first edge of the signal is synchronized with a first clock and the synchronized first edge of the signal is passed to an output. The synchronization results in a delay of the first edge of the signal. The second edge of the signal is passed to the output. The passed second edge of the signal has a delay that is less than the delay of the first edge of the signal by at least one clock cycle of the first clock.

A scan line to which a selection signal or a non-selection signal is input from its end, and a transistor in which a clock signal is input to a gate, the non-selection signal is input to a source, and a drain is connected to the scan line are provided. A signal input to the end of the scan line is switched from the selection signal to the non-selection signal at the same or substantially the same time as the transistor is turned on. The non-selection signal is input not only from one end but also from both ends of the scan line. This makes it possible to inhibit the potentials of portions in the scan line from being changed at different times.

The invention discloses a GOA circuit, a display device and a drive method of a GOA circuit, the GOA circuit is set to be GOA units including a plurality of levels, a N leveled GOA unit is applied to charge a N leveled scanning line of a display region of the display device, the N leveled scanning line is connected to a first gate all on signal and a second gate all on signal, which can guarantee scanning lines corresponding to all the GOA units are being charged under control of the first gate all on signal and the second gate all on signal. The invention can carry out an all gate on function according to the method above.