A highly reliable semiconductor device is provided. A semiconductor device includes a shift register including a pulse output circuit formed using transistors having the same conductivity type, or the like. A transistor including a back gate is used as a transistor in which a potential difference between a source and a drain is not generated and positive stress is applied to a gate in a non-selection period of the pulse output circuit. In the non-selection period, stress applied to the transistors is reduced by interchanging the potentials of the gates and those of the back gates.

The present disclosure relates to the display technologies, which provides a GOA unit, a GOA circuit, a display driving circuit and a display device, for outputting a gate driving signal and a reset signal of a pixel electrode through a GOA unit, to simplify the display driving circuit. The GOA unit comprises a first node control module, a second node control module, a third node control module, a first output module and a second output module, wherein the first output module outputs the gate driving signal under the control of the node voltage of a first node, the node voltage of a second node and a second input signal inputted at a second input terminal; and the second output module outputs the reset signal of the pixel electrode under the control of the node voltage of the second node, the node voltage of the third node and a third input signal inputted at a third signal input terminal.

A display device includes a display panel having a curved side or a polygonal side, the display panel including a plurality of pixels in a display region, a gate driver including a plurality of normal stages connected to each other for outputting gate signals to the pixels via a plurality of gate lines, and a plurality of dummy stages between some of the normal stages, and a data driver providing data signals to the pixels via a plurality of data lines.

A display panel and a display device are disclosed. The display panel includes an array substrate (21) and a driving IC (11). The array substrate (21) includes a shift register (211). The shift register (211) includes a plurality of shift register units (2111) which are connected in multi stages. The array substrate (21) further includes a charge pump (22) which is connected with each of the shift register units (2111). An input terminal of the charge pump (22) is connected with the driving IC (11). An output terminal of the charge pump (22) is connected with each of the shift register units (2111). According to the disclosure, a charge pump is disposed on the array substrate, so as to lower a cost of the display panel.

A Gate Driver on Array (GOA) circuit is disclosed. The GOA circuit comprising: a drive line scan control signal generation unit operative to generate a drive line scan clock signal and a drive line scan pulse signal; multiple GOA groups operative to acquire the drive line scan clock signal, to generate GOA group output signals sequentially according to GOA group input signals, wherein the GOA group output signal generated by one of the GOA groups is the GOA group input signal of a next GOA group to realize a shift register function of the multiple GOA groups; multiple drive line scan signal generation modules operative to acquire GOA group output signals and drive line scan pulse signal, and to generate drive line scan signals sequentially; multiple gate line groups operative to be applied with the drive line scan signals, to complete drive line scan for the multiple gate line groups sequentially.

The present disclosure provides a shift register unit, a gate driving circuit and a display apparatus. The shift register unit comprises: a first latch module having a first input terminal connected to a first clock signal terminal or a second clock signal terminal, a second input terminal for receiving a pulse signal, and an output terminal; and a second latch module having a first input terminal connected to the first clock signal terminal or the second clock signal terminal, a second input terminal connected to the output terminal of the first latch module, and an output terminal connected to a signal output terminal of the shift register unit. The first input terminal of the first latch module and the first input terminal of the second latch module are connected to the same signal terminal.

A gate drive circuit and a display device are provided. The present disclosure pertains to the technical field of display technology and solves the technical problem of wide frame of the existing display device. The shifting register is configured to output primary drive signal into a first follower and a second follower in consecutive first scanning period t1 and second scanning period t2. The first follower is configured to output gate drive signal to a first gate line in t1 under the driving of the primary drive signal; and the second follower is configured to output the gate drive signal to a second gate line in t2 under the driving of the primary drive signal. The present disclosure can be applied to display devices, such as liquid crystal display devices and OLED display devices, and the like.

A driving circuit comprises a plurality of shift register (SR). An i.sup.th SR among the plurality SR's comprises a resetting circuit, an input switch, a capacitor, and an output circuit. The resetting circuit is used for adjusting a resetting voltage according to a control voltage. The input switch is used for adjusting the control voltage according to an (i2).sup.th driving signal from an (i2).sup.th SR among the plurality of SR's, selectively. The capacitor is used for adding a voltage variation of a boosting signal to the control voltage. The output circuit is used for taking an i.sup.th input signal as an i.sup.th output signal according to the control voltage and the resetting voltage, selectively. The positive edge of the boosting voltage leads the negative edge of the i.sup.th input signal.

There are provided a shift register unit, a strobe driving circuit, a display apparatus and a driving method for the shift register unit. The shift register unit comprises: an inputting module (10) configured to control a potential of the pulling-up control node according to a signal of the first signal input terminal; a pulling-up module (20) configured to output a present stage output signal from the present stage output terminal according to a signal of the second clock signal terminal and the potential of the pulling-up control node; a pulling-down module (30) configured to pull down the potential of the pulling-up control node and the signal of the present stage output terminal to a low level according to a signal of the third clock signal terminal; a resetting module (40) configured to reset the potential of the pulling-up control node according to a signal of the second signal input terminal and pull down the signal of the present stage output terminal to a low level. Correspondingly, the pulling-down operation of the shift register unit is implemented in a simple manner, so that a number of TFTs as required, power consumption and wiring are reduced.

A shiftable memory supporting in-memory data structures employs built-in data shifting capability. The shiftable memory includes a memory having built-in shifting capability to shift a contiguous subset of data from a first location to a second location within the memory. The shiftable memory further includes a data structure defined on the memory to contain data comprising the contiguous subset. The built-in shifting capability of the memory to facilitate one or more of movement of the data, insertion of the data and deletion of the data within the data structure.