A shift register group includes a plurality of series-coupled shift registers each being configured to provide an output signal. The third control signal of a first sift register of the plurality of shift registers is the output signal provided by the shift register N stages after the first shift register, and the fourth control signal of the first sift register is the voltage at the driving node of the shift register 2N stages after the first shift register, wherein N is a natural number. A driving method of the aforementioned shift register group is also provided.

A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

A display substrate includes at least one scan driving circuit. The scan driving circuit includes a first voltage signal line, a second voltage signal line, a third voltage signal line, and shift registers. A shift register includes: first and second transistors disposed between the first voltage signal line and the second voltage signal line, third and fourth transistors disposed between the second voltage signal line and the third voltage signal line, at least one first scan signal line electrically connected to a first output terminal, and at least one second scan signal line electrically connected to a second output terminal. A second electrode of the first transistor and a second electrode of the second transistor are both electrically connected to the first output terminal; a second electrode of the third transistor and a second electrode of the fourth transistor are both electrically connected to a second output terminal.

A shift register group includes a plurality of series-coupled shift registers each being configured to provide an output signal. The third control signal of a first sift register of the plurality of shift registers is the output signal provided by the shift register N stages after the first shift register, and the fourth control signal of the first sift register is the voltage at the driving node of the shift register 2N stages after the first shift register, wherein N is a natural number. A driving method of the aforementioned shift register group is also provided.

A scan driver includes a plurality of stages to receive one or more clock signals, each of the plurality of stages to supply a carry signal to a corresponding first output terminal and to supply a scan signal to a corresponding second output terminal, corresponding to a voltage of a corresponding first node, and each of the plurality of stages including a reset unit, the reset unit to initialize the first node, the first output terminal, and the second output terminal, corresponding to a gate start pulse supplied to a corresponding reset input terminal.

A scan driver includes a plurality of stages configured to supply scan signals to scan lines. An ith (i is a natural number) stage of the stages at one side of a panel includes: a first transistor connected between a first input terminal and a first node, and including a gate electrode connected to a second input terminal; a second transistor connected between a third input terminal and a first output terminal for outputting an ith scan signal of the scan signals, and including a gate electrode connected to the first node; a third transistor connected between the first output terminal and a first power input terminal configured to receive a first off voltage, and including a gate electrode connected to the second input terminal; and a first capacitor connected between the first node and the first output terminal.

A gate drive circuit is disclosed. The drive circuit includes M cascaded shift registers, where M is a natural number, and a clock controller configured to generate two reverse-phase clock signals. The drive circuit also includes a high level controller configured to generate a high level signal, and a low level controller configured to generate a low level signal, where one of the high level controller and the low level controller is configured to generate an initial pulse signal during an initial stage. The drive circuit also includes a start unit cascaded with the M shift registers, where the start unit is configured to provide a start signal to the shift registers.

An amorphous silicon gate driving circuit includes multiple cascaded shift registers. Each of the shift registers includes a shift register unit, which contains multiple TFTs and multiple capacitors, an N-th output terminal GN, an (N+1)-th output terminal GN+1, a high voltage signal terminal Vgh and a low voltage signal terminal Vgl; and an output control unit having an N-th additional output terminal. The output control unit is configured to control a time period during which the N-th additional output terminal outputs a high voltage level to be within a time period during which the N-th output terminal outputs the high voltage level, where a signal falling edge for turning off TFTs at a former one of two adjacent rows of pixel units is completely separated from a signal rising edge for turning on TFTs at a latter one.

The present invention provides a shift register and a driving method thereof, a gate driving device and a display panel, such that the shift register can pull down the output terminal by means of DC voltage signals, which reduces the duty cycle of the clock signal and thereby lowers the power consumption of Thin Film Transistors. The shift register comprises a plurality of cascaded shift register elements, each of which comprises: an input module in response to the input signal outputted by an input signal terminal, an output module in response to a voltage signal outputted a the pull-up node, a reset module in response to the reset signal outputted by a reset signal terminal, a first pull-down module in response to the input signal and the reset signal, and a second pull-down module in response to a voltage signal of a pull-down node.

An integrated circuit die stack and method thereof are described herein that is capable of detecting a physical tampering event. The integrated circuit die stack includes a first integrated circuit die including a sensor network that extends substantially across an entire top surface of the first integrated circuit die, and a second integrated circuit die stacked below the first integrated circuit die. The second integrated circuit die is configured to receive sensing signals generated by the sensor network via a plurality of through-silicon-vias coupled with the first integrated circuit die and the second integrated circuit die.