The present disclosure relates to a scan driver circuit including clock signal lines and cascaded shift registers. The shift registers include an input sub-circuit, a first control sub-circuit, a second control sub-circuit and an output sub-circuit. The input sub-circuit is connected to a starting signal terminal, a first node and a first signal terminal. The first control sub-circuit is connected to the first signal terminal, the first node and a second node. The second control sub-circuit is connected to the first node, the second node, a second voltage terminal and a third signal terminal. The output sub-circuit is connected to the first node, the second node, an output terminal, a second signal terminal and the second voltage terminal. The second signal terminal and the third signal terminal of the same shift register are connected to different clock signal lines.

A shift register unit including an input circuit configured to receive a first clock signal and an input signal to provide the input signal to a first node; a first control circuit electrically connected to the first node and a second node and configured to receive the first clock signal to control a voltage of the second node; an output circuit electrically connected to the first node and an output terminal and configured to receive a second clock signal to provide an output signal to the output terminal based on the second clock signal; an output voltage control circuit electrically connected to the second node and the output terminal and configured to control a voltage of the output signal; and a discharge circuit electrically connected to the first node and the second node and configured to receive the second clock signal to achieve electrical discharge of the first node.

A display device with a variant-shape display region other than the rectangular display region is configured to form a scanning line drive circuit along the variant-shape display region. The scanning line drive circuit includes bus wiring group with clock wiring for supplying clocks with three or more phases and the power supply wiring for supplying power, and the unit circuits for configuring the shift register including five or more transistors. The bus wiring and the unit circuits are formed on the different regions so as not to cross with one another.

A shift register includes a shift module configured for causing the cascade signal output end to output a cascade signal in response to a signal of the input signal end; an reverse output module configured for causing the reverse signal output end to output a signal reverse to the cascade signal output end in response to a signal of the cascade signal output end; a latch module configured for causing an output end of the latch module to output a control signal of the masking signal end in response to signals of the cascade signal output end and the reverse signal output end of a previous level; and a selection output module configured for providing a signal of the first power supply end or the second power supply end to the driving signal output end in response to a signal of the output end of the latch module.

A display panel including a display region including first and second display regions, and sub-pixels in the display region, data lines electrically connected to the sub-pixels and including first data lines in the first display region and second data lines located in the second display region; a shift register in the first display region and including cascaded shift units, each shift unit being divided into at least two sub-units, and one sub-unit being located at a side of one sub-pixel connecting lines electrically connected to the sub-units of the shift units, one of the first data lines overlapping with one of the connecting lines in a direction perpendicular to a plane of the display panel; and compensation structures located in the second display region, and each overlapping with at least one of the second data lines in the direction.

Provided is a shift register unit. The shift register unit includes: a first input circuit, coupled to a first clock terminal, an input terminal, a first node and a second node; a second input circuit, coupled to the first node, the first clock terminal, a first power terminal and a third node; a first control circuit, coupled to the input terminal, the first clock terminal, the second node, a second power terminal, a second clock terminal and the third node; a second control circuit, coupled to the third node, the second clock terminal, the first node, the first power terminal, the second power terminal, a fourth node and a fifth node; and an output circuit, coupled to the fourth node, the fifth node, the first power terminal, the second power terminal and an output terminal.

An electronic device includes a substrate, a first transistor, a second transistor, an electronic unit and a conductor. The first transistor is disposed on the substrate and comprises an oxide semiconductor layer. The second transistor is disposed on the substrate and comprises a silicon semiconductor layer. The electronic unit is disposed on the substrate and electrically connected to the second transistor. The conductor is electrically connected to the oxide semiconductor layer and the silicon semiconductor layer.

The present disclosure provides a gate driving circuit and a display panel. The display panel includes a display area and a peripheral area surrounding the display area. At least one gate driving circuit is arranged in the peripheral area. The at least one gate driving circuit includes a plurality of shift register units cascaded in sequence. The plurality of shift register units include first shift register units and second shift register units. The first shift register units and the second shift register units are spaced apart from each other. The number of transistors in the first shift register units is smaller than the number of transistors in the second shift register units.

Provided is a gate drive circuit, including a plurality of shift registers and buffers in cascade, wherein each of the shift registers is configured to output a first gate scanning signal stage by stage according to a preset scanning timing; and each of the buffers is configured to perform waveform inversion on the first gate scanning signal for a plurality of times to convert the first gate scanning signal into a second gate scanning signal, wherein falling edge time of the second gate scanning signal is less than falling edge time of the first gate scanning signal.

A driving circuit includes a first node control circuit, a second node control circuit and a first output circuit; the second node control circuit is configured to control to connect the first node and the second node under the control of a low voltage signal provided by the first low voltage input terminal; the first node control circuit is configured to control to connect the first node and the second low voltage input terminal under the control of a first clock signal provided by the first clock signal line; the first output circuit is configured to control to connect the driving signal output terminal and the third low voltage input terminal under the control of a potential of the pull-down node; at least two of the first low voltage input terminal, the second low voltage input terminal and the third low voltage input terminal are different from each other.