The present invention provides a liquid crystal display panel and a gate drive circuit thereof. The gate drive circuit comprises a plurality of shift register circuit, and the plurality of shift register circuit are series cascade connected, and each shift register circuit comprises: a first pull-up holding circuit, coupled to the first node, the first clock signal, a first reference voltage and a second reference voltage, and employed to keep a low voltage level of the first node; a compensating circuit, coupled to the first node or the first pull-up holding circuit, and employed to compensate the voltage level of the first node or the first pull-up holding circuit. Thereby, the stability of long-term operation of the gate drive circuit can be promoted to raise the quality of the display panel.

An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

Various embodiments comprise apparatuses to assign unique device identifier values to addressable devices in a stacked package. In one embodiment, an apparatus is disclosed including a stacked package with at least two addressable devices. Each of the addressable devices includes data input and switch path circuitry, a shift register coupled to the data input and switch path circuitry, and a single through-substrate via (TSV) through which the unique device identifier values can be assigned. The single TSV is coupled to the data input and switch path circuitry and between adjacent ones of the at least two addressable devices. Additional apparatuses, systems, and methods are described.

The present disclosure relates to display technology, and provides an inverter, a gate driving circuit and a display apparatus, capable of solving the problem that it is difficult to apply Scan Power technology in the display apparatus since a power signal outputted from the inverter has a small current. The inverter comprises: a current amplification module configured to amplify a current of the output terminal of the inverter based on a signal at a first clock signal terminal, a signal at a second clock signal terminal, a signal at a third clock signal terminal, a signal at a fourth clock signal terminal, a signal at a first input signal terminal, and a signal at a second input signal terminal, and to control the output terminal of the inverter to output a high level signal; and a pull-down module configured to control the output terminal of the inverter to output a low level signal. The inverter according to the present disclosure may be applied in a display apparatus employing the Scan Power technology.

A gate drive circuit and a display panel. The gate drive circuit includes one or more shift register groups. Each of the shift register groups includes N shift adjacent registers that output in sequence, with N being an integer greater than or equal to 3. Each of the shift registers includes a first output stage and a frequency division control module. The first output stage is configured to output a gate drive signal. The frequency division control module is configured to control outputting of the gate drive signal based on a refresh frequency. A control end of each frequency division control module in each of the shift register groups receives a control signal with a different phase and a same frequency, respectively, to adjust a pulse width of the gate drive signal and maintain a same pulse width at different refresh frequencies.

Disclosed are a shift register unit (SRn), a drive control circuit, a display apparatus and a driving method. The shift register unit includes an input circuit, a control circuit, a first output circuit a second output circuit, and a noise reduction circuit configured, in response to a signal from the noise reduction signal terminal (VEL), to provide a signal from a third reference voltage signal terminal (V3) to the second node (N2) and to control the second output circuit to stop signal output.

Disclosed is a shift register, comprising: a first control sub-circuit, which provides a signal of a signal input end for a first node; a second control sub-circuit, which provides a signal of a second power source end or a signal of the first clock signal end for the second node; a third control sub-circuit, which provides a signal of the second clock signal end or a signal of the first power source end for a fourth node and maintains the potential of the fourth node; a first output sub-circuit, which provides the signal of the first power source end or the signal of the second power source end for a first signal output end; and a second output sub-circuit, which provides the signal of the first power source end or the signal of the second power source end for a second signal output end.

The present invention provides a GOA circuit based on LTPS semiconductor TFT, comprising a plurality of GOA units which are cascade connected, and N is set to be a positive integer and an Nth GOA unit comprises a pull-up control part (100), a pull-up part (200), a first pull-down part (400) and a pull-down holding part (500); the pull-down holding part (500) utilizes a high/low voltage reverse design and comprises a first, a second and a third DC constant low voltage levels (VSS1, VSS2, VSS3) which are sequentially abated and a DC constant high voltage level (H), the influence of electrical property of the LTPS semiconductor TFT to the GOA driving circuit, and particularly the bad function due to the electric leakage issue can be solved; meanwhile, the existing issue that the second node voltage level and the pull-down holding circuit part in the GOA circuit based on the LTPS semiconductor TFT cannot be at higher voltage level in the non-functioning period can be solved to effectively maintain the first node (Q(N)) and the output end (G(N)) at low voltage level.

The disclosure provides a shift register, a gate driving circuit, a display panel and a display apparatus. The shift register may comprise an inputting module, a resetting module, a pulling up module, a pulling down module for a first node, a pulling down module for a second node, an output controlling module and an output noise reducing module. The inputting module is used to pull up a potential of the first node. The resetting module is used to pull down the potential of the first node. The pulling up module is used to pull up the potential of the second node. The pulling down module for the first node is used to pull down the potential of the first node. The pulling down module for the second node is used to pull down the potential of the second node. The output controlling module is used to control the scanning signal outputting terminal to output a signal from the second clock signal terminal; and to connect the low level signal terminal with the third node, which can ensure that the shift register can output a scanning signal in a corresponding period. Meanwhile, the signal from the third node is noise reduced by the output noise reducing module and then outputted to the scanning signal outputting terminal, which can reduce the noise of the signal outputted from the scanning signal outputting terminal.

A shift register and a display device are provided. The shift register includes a pre-charge unit, a pull-up unit, a first pull-down unit and a second pull-down unit. The pre-charge unit receives first and second input signals, and outputs a pre-charge signal via a first node. The pull-up unit receives a pre-charge signal and a clock signal, and outputs a scanning signal via a second node. The first pull-down signal receives the pre-charge signal, first and second pull-down control signals, and controls whether to pull-down the scanning signal to a reference voltage level. The second pull-down signal receives the pre-charge signal and first and second pull-down control signals, and controls whether to keep the scanning signal at the reference voltage level. The period of the first second pull-down control signal and the period of the second pull-down control signal are in a range from 12 frames to 180 frames.