A shift register, a driving circuit, a driving method and a display device are provided. The shift register includes: an input circuit configured to provide a first voltage or a second voltage to a first node and a light-emitting control signal terminal under control of a first input signal and a second input signal; a processing circuit configured to provide the first voltage or the second voltage to a second node under control of the first input signal and a potential of the first node; and an output circuit configured to provide the first voltage or the second voltage to a first output scanning signal terminal under control of a first clock signal and the potential of the first node, and provide the first voltage or the second voltage to a second output scanning signal terminal under control of a potential of the first output scanning signal terminal.

A touch display device, a display panel, and a gate driving circuit are disclosed. A touch display device comprises a display panel having subpixels, a gate driving circuit including gate stages for applying a scan signal to the display panel through gate lines and dummy stages selectively disposed between the gate stages, and a touch driving circuit applying a touch driving signal to the display panel through touch lines and receiving a touch sensing signal generated by the display panel, wherein the dummy stages are divided into two or more dummy stage groups, and wherein a group control signal line for applying a group control signal based on dummy stage group and an individual control signal line for applying an individual control signal to each dummy stage included in the dummy stage group are disposed along a bezel area.

The present disclosure provides a display device and a display panel. The display panel includes: multiple pixel circuit rows at a side of the substrate, where multiple pixel circuit rows form multiple pixel circuit groups distributed in a column direction, and each pixel circuit group includes at least one pixel circuit row; a gate drive circuit, including multiple shift registers, where at least one shift register is between two adjacent pixel circuit groups. Each of the shift register includes: an output sub-circuit, connected with a first node and a second node, configured to perform output based on potentials of the first node and the second node; and an input sub-circuit, connected with multiple clock signal lines to control the potentials of the first node and the second node based on potentials of multiple clock signal lines.

A shift register unit, a gate drive circuit, a display apparatus and a driving method. The shift register unit includes: a first control circuit, configured to control a signal of a first node and a signal of a second node according to a signal of an input signal end and a signal of a first clock signal end; second control circuits, configured to control signals of at least two drive nodes according to the signal of the first node, the signal of the second node and signals of second clock signal ends; cascade output circuits, configured to provide the signal of one of the at least two drive nodes to a cascade output end according to cascade selection signal ends; and drive output circuits, configured to provide the signal of at least one of the at least two drive nodes to drive output ends corresponding to the drive nodes.

A display substrate includes a base substrate including a display area and a peripheral area on at least one side of the display area; a pixel array, located in the display area and including multiple pixel units; and, a scan driving module, located in a driving circuit area of the peripheral area, and including multiple shift register units, multiple signal lines being arranged in one shift register units, and extending along a first direction; wherein a ratio of a sum W1 of widths of the multiple signal lines in a second direction to a width W2 of the shift register unit in the second direction is W1/W2, and a length of at least one pixel unit along the first direction is a pixel pitch value; the first direction intersects the second direction; a product of W1/W2 and the pixel pitch value is greater than 18 um and less than 40 um.

A display panel includes a driver circuit including shift registers with N stages and being cascade with each other, where N2, and each shift register includes a first control portion and a second control portion. The first control portion is configured to control a first output signal, where the first output signal of an i-th stage of shift register is an input signal of a j-th stage of shift register, and 1iN, 1jN. The second control portion is configured to receive at least the first output signal and a frequency control signal and control a second output signal. In a case where the first output signal is an effective pulse and a time period of the effective pulse is within a time period of an effective pulse of the frequency control signal, the second output signal is the effective pulse.

A display device includes a substrate having a display region in which a plurality of pixels are arrayed in a first direction and a second direction different from the first direction, a plurality of scanning lines coupled to the pixels arrayed in the first direction, a plurality of signal lines coupled to the pixels arrayed in the second direction, a gate driver configured to supply a scanning signal to the scanning lines, and a signal line selection circuit configured to supply a pixel signal to the signal lines.

A display substrate is disclosed, including a display area and a non-display area. The non-display area has a gate drive circuit including multiple cascaded shift register units. A shift register unit includes an input control circuit and an output circuit. The input control circuit is electrically connected to a clock signal line group, a first power supply line, a second power supply line and an output circuit, the output circuit is electrically connected to the first power supply line and a second power supply line. The input control circuit at least includes an input circuit and a first control circuit. The clock signal line group, the second power supply line, the input control circuit, the output circuit and the first power supply line are arranged sequentially along a first direction. The input circuit is located between the second power supply line and the first control circuit in the first direction.

The present invention provides a liquid crystal display that can reduce occurrence of quality problems and improve adhesive strength between substrates. The present invention is a liquid crystal display including a first substrate, a second substrate, and a seal. The first substrate includes a shift register monolithically formed on an insulating substrate, a plurality of bus lines, a first end, and a display region. The shift register includes a plurality of multistage-connected unit circuits and wiring connected to the plurality of unit circuits, and is arranged in a region between the first end and the display region. At least one of the unit circuits includes a clock terminal, an output terminal, an output transistor, a second transistor, and a bootstrap capacitor. The output transistor and the bootstrap capacitor are arranged in a region between the first end and one of the wiring and the second transistor.

A gate driving circuit and a method for driving a gate driving circuit, a display panel, and a display device are provided. The gate driving circuit includes M groups of shift register units, and each group includes one first shift register unit and N1 second shift register units. The first noise reduction of the first shift register unit performs noise reduction under control of the second node. The second noise reduction circuit of the second shift register units performs noise reduction under control of the second node. In a same group of shift register units, the first shift register unit and the second shift register units share a same second node. A first input signal and a second input signal received by a Kth group of shift register units are a shift signal of a first shift register unit in a (K2)th group of shift register units.