An apparatus that includes a shift register unit, a gate driving circuit, and a display apparatus. The shift register unit includes: an input circuit, a reset circuit, a node control circuit, a cascade output circuit and a drive output circuit, where the drive output circuit is configured to provide the signal of the clock signal end to a drive output end in response to the signals of the first node.

A display baseplate includes a first gate driving circuit, a second gate driving circuit, and a plurality of pixel driving circuits arranged in array. The first gate driving circuit includes a plurality of first shift registers cascaded to each other, the second gate driving circuit includes a plurality of second shift registers cascaded to each other, and the plurality of pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit located in different rows, a write control terminal of the first pixel driving circuit and a write control terminal of the second pixel driving circuit are connected to different first shift registers, and a compensation control terminal of the first pixel driving circuit and a compensation control terminal of the second pixel driving circuit are connected to a same second shift register.

A gate driver circuit includes multiple stages of shift registers. These shift registers are cascade connected in series. Each stage of the shift registers includes a scan unit, a control unit and an output unit. The scan unit receives an enable signal. The scan unit is triggered by a clock signal to sample the enable signal, so as to generate a first node voltage. The first node voltage is utilized as a shift output signal transmitted to a subsequent shift register. The control unit receives a multiple-area-frame-rate control signal. According to the multiple-area-frame-rate control signal, the control unit selectively blocks the first node voltage and outputs the second node voltage. The output unit selectively transmits or suspends transmitting gate driver signals to a pixel circuit on a display panel according to the second node voltage.

The present disclosure relates to a scan driver circuit including clock signal lines and cascaded shift registers. The shift registers include an input sub-circuit, a first control sub-circuit, a second control sub-circuit and an output sub-circuit. The input sub-circuit is connected to a starting signal terminal, a first node and a first signal terminal. The first control sub-circuit is connected to the first signal terminal, the first node and a second node. The second control sub-circuit is connected to the first node, the second node, a second voltage terminal and a third signal terminal. The output sub-circuit is connected to the first node, the second node, an output terminal, a second signal terminal and the second voltage terminal. The second signal terminal and the third signal terminal of the same shift register are connected to different clock signal lines.

A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of on/off of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/m (110.sup.18 A/m) or less. Therefore, the drive capability of the semiconductor device can be improved.

A display substrate includes: a base substrate; light-emitting elements located in a display area; pixel driving circuits located respectively connected to the light-emitting elements, each pixel driving circuit including an N-type transistor and a P-type transistor; a first gate driving circuit, a second gate driving circuit and a third gate driving circuit in a border area of the display area, the first and third gate driving circuits being connected with the P-type transistor, the second gate driving circuit being connected with the N-type transistor, and orthographic projections of the first to third gate driving circuits on the base substrate are not overlapped with each other; and a planarization layer located between the pixel driving circuits and the light-emitting elements.

A shift register unit including an input circuit configured to receive a first clock signal and an input signal to provide the input signal to a first node; a first control circuit electrically connected to the first node and a second node and configured to receive the first clock signal to control a voltage of the second node; an output circuit electrically connected to the first node and an output terminal and configured to receive a second clock signal to provide an output signal to the output terminal based on the second clock signal; an output voltage control circuit electrically connected to the second node and the output terminal and configured to control a voltage of the output signal; and a discharge circuit electrically connected to the first node and the second node and configured to receive the second clock signal to achieve electrical discharge of the first node.

A shift register unit, a display driving circuit, a display panel, and a control method. The shift register unit includes: an input circuit configured to provide signals of an input signal terminal (IN) and a power signal terminal (VGH) to first and second pull-up nodes (Q1, Q2); a first control circuit configured to control potentials of the first pull-down node (QB1), and the first pull-up node (Q1); a second control circuit configured to control potentials of the second pull-up node (Q2) and the second pull-down node (QB2) based on the first pull-up node (Q1) and the first pull-down node (QB1); and an output circuit configured to provide the signal of one of the power signal terminal (VGH) and the reference signal terminal (VGL) to an output signal terminal (OUT) under control of the second pull-up node (Q2) and the second pull-down node (QB2).

Gate driving circuit, display panel and display device are provided. The gate driving circuit includes a plurality of cascaded shift registers. A shift register of the plurality of shift registers includes an input module, a node control module, a first coupling module, a second coupling module and an output module. The input module is configured to adjust potentials of a first node and a second node. The node control module is configured to adjust potentials of a third node and a fourth node. The first coupling module includes a first switch unit and a first capacitor. The second coupling module includes a second capacitor placed between, and connected to, the fourth node and a shift output end. The output module is configured to control a signal at the shift output end. A capacitance of the second capacitor differs from a capacitance of the first capacitor.

A display panel includes pixel driving circuits distributed in an array and forming pixel driving circuit groups, each pixel driving circuit group includes pixel driving circuit rows with each including pixel driving circuits, each of which includes a driving circuit connected to a first, second and third nodes, to input a driving current to the third node through the second node in response to a signal of the first node; a first switching unit with a first end connected to a first power supply terminal and second end connected to the second node, to connect the first power supply terminal and the second node in response to a pulse width modulation signal; in a same pixel driving circuit group, a second end of any first switching unit is connected to a second end of at least one first switching unit in each of the other pixel driving circuit rows.