The present application discloses a display panel, a driving chip, and a display apparatus. The display panel includes a gate driving circuit including a plurality of shift registers in a cascaded connection, and the shift register includes a first transistor that is provided with a power supply voltage through a resistor structure.

A gate driving circuit includes stages, where each stage of the gate driving circuit includes a second transistor connected between a first node and a second node and which includes a first gate connected to a second terminal through which a first voltage is supplied and a second gate connected to a third terminal through which a second voltage is supplied, a fourth transistor connected between the second terminal and an output terminal and which includes a first gate connected to the second node and a second gate connected to the third node, a first capacitor connected between the second node and the output terminal and a second capacitor connected between the third node and the output terminal.

Gate driving circuit, display panel and display device are provided. The gate driving circuit includes a plurality of cascaded shift registers. A shift register of the plurality of shift registers includes an input module, a node control module, a first coupling module, a second coupling module and an output module. The input module is configured to adjust potentials of a first node and a second node. The node control module is configured to adjust potentials of a third node and a fourth node. The first coupling module includes a first switch unit and a first capacitor. The second coupling module includes a second capacitor placed between, and connected to, the fourth node and a shift output end. The output module is configured to control a signal at the shift output end. A capacitance of the second capacitor differs from a capacitance of the first capacitor.

A display device with a variant-shape display region other than the rectangular display region is configured to form a scanning line drive circuit along the variant-shape display region. The scanning line drive circuit includes bus wiring group with clock wiring for supplying clocks with three or more phases and the power supply wiring for supplying power, and the unit circuits for configuring the shift register including five or more transistors. The bus wiring and the unit circuits are formed on the different regions so as not to cross with one another.

A shift register includes shift units. The shift unit includes: first output module for writing signal of first high potential line into output terminal when first node is at high level; second output module for writing signal of low potential line into output terminal when second node is at high level; first control module for writing signal to first node; and second control module for writing signal to second node. The first control module includes first unit and first transistor; first unit is configured to write signal of input terminal into third node in response to signal provided by first clock terminal; gate of first transistor is electrically connected to second high potential line. The second high potential line provides second high potential signal, and voltage value of second high potential signal is smaller than voltage value of high level in signal provided by input terminal.