A shift register unit, a gate driving circuit and a display device are disclosed. The shift register unit includes a shift register and a voltage adjusting circuit. The voltage adjusting circuit is coupled to a set node of the shift register. In a working process, the voltage adjusting circuit is configured to adjust a voltage of the set node in response to a signal of a first clock signal terminal.

An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.

A shift register and a driving method therefor, a display substrate and a display apparatus. The shift register comprises: a first control sub-circuit, which provides a signal of a signal input end for a first node under the control of a first clock signal end, a second clock signal end, a second node and a first power source end; a second control sub-circuit, which provides a signal of a second power source end or a signal of the first clock signal end for the second node under the control of the first clock signal end and the first node; a third control sub-circuit, which provides a signal of the second clock signal end or a signal of the first power source end for a fourth node and maintains the potential of the fourth node under the control of the second clock signal end, the first node and the second node.

The present disclosure provides a display panel and a driving method. The display panel includes a display region, including a plurality of scan lines, and a non-display region. The non-display region includes a first non-display region including a trigger signal line, a plurality of first-clock signal lines from a first first-clock signal line to a k-th first-clock signal line, a plurality of second-clock signal lines from a first second-clock signal line to a k-th second-clock signal line, and n levels of cascaded shift registers; the plurality of first-clock signal lines is electrically connected to k levels of shift registers in sequence, respectively; the plurality of second-clock signal lines is electrically connected to the k levels of shift registers in sequence, respectively; and the trigger signal line is electrically connected to shift registers from a first level to a k-th level and from an (nk+1)-th level to an n-th-level.

The present disclosure provides a display panel and a driving method. The display panel includes a display region, including a plurality of scan lines, and a non-display region. The non-display region includes a first non-display region including a trigger signal line, a plurality of first-clock signal lines from a first first-clock signal line to a k-th first-clock signal line, a plurality of second-clock signal lines from a first second-clock signal line to a k-th second-clock signal line, and n levels of cascaded shift registers; the plurality of first-clock signal lines is electrically connected to k levels of shift registers in sequence, respectively; the plurality of second-clock signal lines is electrically connected to the k levels of shift registers in sequence, respectively; and the trigger signal line is electrically connected to shift registers from a first level to a k-th level and from an (nk+1)-th level to an n-th-level.

Provided is a gate drive circuit, including a plurality of shift registers and buffers in cascade, wherein each of the shift registers is configured to output a first gate scanning signal stage by stage according to a preset scanning timing; and each of the buffers is configured to perform waveform inversion on the first gate scanning signal for a plurality of times to convert the first gate scanning signal into a second gate scanning signal, wherein falling edge time of the second gate scanning signal is less than falling edge time of the first gate scanning signal.

A display device with a variant-shape display region other than the rectangular display region is configured to form a scanning line drive circuit along the variant-shape display region. The scanning line drive circuit includes bus wiring group with clock wiring for supplying clocks with three or more phases and the power supply wiring for supplying power, and the unit circuits for configuring the shift register including five or more transistors. The bus wiring and the unit circuits are formed on the different regions so as not to cross with one another.

A display baseplate includes a first gate driving circuit, a second gate driving circuit, and a plurality of pixel driving circuits arranged in array. The first gate driving circuit includes a plurality of first shift registers cascaded to each other, the second gate driving circuit includes a plurality of second shift registers cascaded to each other, and the plurality of pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit located in different rows, a write control terminal of the first pixel driving circuit and a write control terminal of the second pixel driving circuit are connected to different first shift registers, and a compensation control terminal of the first pixel driving circuit and a compensation control terminal of the second pixel driving circuit are connected to a same second shift register.

A display panel, a display device, and a driving control method. The display panel includes a shift register unit and output control signal lines coupled to the shift register unit. The output control signal lines are arranged between the shift register unit and a display region of the display panel. The shift register unit includes: a shift register, which is configured to output a cascade signal by a cascade output end; and an output circuit, which is coupled to the shift register, the output circuit being configured to control, according to a signal of an output control signal end and a signal of a first reference signal end, a driving output end to output a gate scanning signal; an output control signal end is coupled to one of output control signal lines.

Display panel and display device are provided. The display panel includes a plurality of shift registers in cascade, for generating primary scan signals, primary scan signals output by adjacent shift registers overlapping; a plurality of gating circuits, electrically connected to the plurality of shift registers in a one-to-one correspondence, for generating scan signals, a frequency of a scan signal of the scan signals being less than or equal to a frequency of a primary scan signal of the primary scan signals; control signal lines, including a first control signal line; and a plurality of shift register areas, each of the plurality of shift register areas comprising at least one shift register.