A shift register unit, includes: a first output module and a second output module, configured to output a signal of a clock signal terminal to a signal output terminal under the control of a pull-up control node; an input module, configured to output a voltage of the first power supply terminal to the pull-up control node under the control of a signal of the signal input terminal; a pull-down control module, configured to pull down a signal of the pull-down control node to a voltage of the second power supply terminal under the control of the signal input terminal; a pull-down module, configured to pull down signals of the pull-up control node and the signal output terminal to the voltage of the second power supply under the control of the pull-down control node; and a reset module, configured to output a signal of the first power supply terminal to the pull-down control node under the control of the reset signal terminal. The shift register unit is capable of raising the output capability of the signal output terminal and shortening the falling time of the output waveform. A gate driving circuit and a display apparatus are also provided.

Systems, methods, and apparatus related to memory devices that perform multiplication using logical states of memory cells. In one approach, a memory cell array has memory cells programmed to store weights for performing the multiplication. Voltages are applied to the memory cells. Each voltage represents one or more input bits to be multiplied by one of the weights. Output currents from the memory cells are accumulated in a common bitline. A sum of the output currents is digitized to provide a digital result. The digital results from several bitlines can be shifted based on bit significance and added to provide a final accumulation result from the multiplication.

Systems, methods, and apparatus related to memory devices that perform multiplication using logical states of memory cells. In one approach, a memory cell array has memory cells programmed to store weights for performing the multiplication. Voltages are applied to the memory cells. Each voltage represents one or more input bits to be multiplied by one of the weights. Output currents from the memory cells are accumulated in a common bitline. A sum of the output currents is digitized to provide a digital result. The digital results from several bitlines can be shifted based on bit significance and added to provide a final accumulation result from the multiplication.

The present invention provides a shift register and a driving method thereof, a gate driving device and a display panel, such that the shift register can pull down the output terminal by means of DC voltage signals, which reduces the duty cycle of the clock signal and thereby lowers the power consumption of Thin Film Transistors. The shift register comprises a plurality of cascaded shift register elements, each of which comprises: an input module in response to the input signal outputted by an input signal terminal, an output module in response to a voltage signal outputted a the pull-up node, a reset module in response to the reset signal outputted by a reset signal terminal, a first pull-down module in response to the input signal and the reset signal, and a second pull-down module in response to a voltage signal of a pull-down node.

Provided are a shift register unit and driving method thereof, a gate driver and a display device, the circuit configuration of the shift register unit can be simplified by disposing, in the shift register unit, the signal input unit for outputting the first level signal or the second level signal to the first terminal of the latch unit under the control of the input signal and the reset signal, the latch unit for latching the signal input from the signal input unit and outputting the latched processed signal to the pull-down unit, the pull-down unit for outputting the first level signal or the second level signal to the signal output unit under the control of the latched processed signal, and the signal output unit for receiving and inverting the signal output from the pull-down signal to generate an output signal and outputting a signal being opposite to the output signal, which is helpful for achieving the narrow bezel of the display panel.

Provided are a shift register unit and driving method thereof, a gate driver and a display device, the circuit configuration of the shift register unit can be simplified by disposing, in the shift register unit, the signal input unit for outputting the first level signal or the second level signal to the first terminal of the latch unit under the control of the input signal and the reset signal, the latch unit for latching the signal input from the signal input unit and outputting the latched processed signal to the pull-down unit, the pull-down unit for outputting the first level signal or the second level signal to the signal output unit under the control of the latched processed signal, and the signal output unit for receiving and inverting the signal output from the pull-down signal to generate an output signal and outputting a signal being opposite to the output signal, which is helpful for achieving the narrow bezel of the display panel.

Systems, methods, and apparatus related to memory devices that perform multiplication using logical states of memory cells. In one approach, a memory cell array has memory cells programmed to store weights for performing the multiplication. Voltages are applied to the memory cells. Each voltage represents one or more input bits to be multiplied by one of the weights. Output currents from the memory cells are accumulated in a common bitline. A sum of the output currents is digitized to provide a digital result. The digital results from several bitlines can be shifted based on bit significance and added to provide a final accumulation result from the multiplication.

Systems, methods, and apparatus related to memory devices that perform multiplication using logical states of memory cells. In one approach, a memory cell array has memory cells programmed to store weights for performing the multiplication. Voltages are applied to the memory cells. Each voltage represents one or more input bits to be multiplied by one of the weights. Output currents from the memory cells are accumulated in a common bitline. A sum of the output currents is digitized to provide a digital result. The digital results from several bitlines can be shifted based on bit significance and added to provide a final accumulation result from the multiplication.

Systems, methods, and apparatus related to memory devices that perform multiplication using logical states of memory cells. In one approach, a memory cell array has memory cells programmed to store weights for performing the multiplication. Voltages are applied to the memory cells. Each voltage represents one or more input bits to be multiplied by one of the weights. Output currents from the memory cells are accumulated in a common bitline. A sum of the output currents is digitized to provide a digital result. The digital results from several bitlines can be shifted based on bit significance and added to provide a final accumulation result from the multiplication.

Systems, methods, and apparatus related to memory devices that perform multiplication using logical states of memory cells. In one approach, a memory cell array has memory cells programmed to store weights for performing the multiplication. Voltages are applied to the memory cells. Each voltage represents one or more input bits to be multiplied by one of the weights. Output currents from the memory cells are accumulated in a common bitline. A sum of the output currents is digitized to provide a digital result. The digital results from several bitlines can be shifted based on bit significance and added to provide a final accumulation result from the multiplication.