The present application relates to a circuit simulation test method and apparatus, a device, and a medium. The method includes: creating a parametric data model, wherein the parametric data model is configured to generate preset write data based on a preset parameter; creating a test platform, wherein the test platform is configured to generate a test result based on the preset write data; creating an eye diagram generation module, wherein the eye diagram generation module is configured to generate a data eye diagram based on the test result; and conducting a simulation test, inputting the preset write data to the test platform and obtaining the test result, and generating the data eye diagram by using the eye diagram generation module.

A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.

An electronic device includes an enable signal generation circuit configured to activate, when a write operation is performed, a termination enable signal earlier than a time point when a write latency elapses, by a duration amount of an entry offset period; and a data input and output circuit configured to receive, when the write operation is performed, data later than the time point when the write latency elapses, based on the termination enable signal, wherein the data input and output circuit receives the data after the write latency elapses by a duration amount of a first data reception delay period.

An electronic device includes an enable signal generation circuit configured to activate, when a write operation is performed, a termination enable signal earlier than a time point when a write latency elapses, by a duration amount of an entry offset period; and a data input and output circuit configured to receive, when the write operation is performed, data later than the time point when the write latency elapses, based on the termination enable signal, wherein the data input and output circuit receives the data after the write latency elapses by a duration amount of a first data reception delay period.

A device may include a ZQ calibration circuit. The ZQ calibration circuit may include a first register configured to store a first impedance code generated responsive to a ZQ calibration command. The ZQ calibration circuit may also include a second register configured to store a shift value. Further, the ZQ calibration code may include a compute block configured to generate a second impedance code based on the first impedance code and the shift value. Systems and related methods of operation are also described.

A method for testing a memory chip includes: in response to read command for the memory chip, controlling clock signal to be kept in first state within first preset time period and at the same time controlling complementary clock signal to be kept in second state within first preset time period; in response to clock signal kept in the first state and complementary clock signal kept in the second state, keeping data strobe signal in the first state within second preset time period and at the same time keeping complementary data strobe signal in the second state within the second preset time period; and when the data strobe signal and the complementary data strobe signal are kept in first and second states respectively, controlling first and second driving modules connected respectively to data strobe terminal and complementary data strobe terminal to operate and measure first and second resistance values respectively.

A computer-implemented method includes fetching, by a controller, data using a plurality of memory channels of a memory system. The method further includes detecting, by the controller, that a first memory channel of the plurality of memory channels has not returned data. The method further includes marking, by the controller, the first memory channel from the plurality of memory channels as unavailable. The method further includes, in response to a fetch, reconstructing, by the controller, fetch data based on data received from all memory channels other than the first memory channel.

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.

A semiconductor memory device includes a memory cell array, first and second pads, an interface circuit connected to the first pad and configured to transmit data input through the first pad to the memory cell array and output data received from the memory cell array through the first pad, a ZQ calibration circuit that is connected to the second pad and executes a ZQ calibration to generate a ZQ calibration value, and a sequencer configured to control the ZQ calibration circuit to apply the ZQ calibration value to the interface circuit. A command set is input through the first pad after reading data from the memory cell array to cause the interface circuit to output the data read from the memory cell array, and the ZQ calibration circuit executes the ZQ calibration after the command set is input and before the data is output through the first pad.

Examples herein relate to devices that include a strobe tree circuit for capturing data using a memory-sourced strobe. In an example, a device includes a data capture path including first and second flip-flops, and a strobe tree including a comparator and first and second multiplexers. The comparator is configured to output complementary signals on first and second output nodes. First and second selection input nodes of the first multiplexer are connected to the first and second output nodes of the comparator, respectively. First and second selection input nodes of the second multiplexer are connected to the second and first output nodes of the comparator, respectively. The read strobe tree is configured to provide first and second signals output from the first and second multiplexers to first and second nodes, respectively. Clock input nodes of the first and second flip-flops are connected to the first and second nodes, respectively.