Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

An apparatus includes a host and a memory device connected to the host through a bus. The bus is used to communicate a data clock controlling data write timing during a write operation executed by the memory device and a read clock controlling data read timing during a read operation executed by the memory device. The memory device performs first duty cycle monitoring that monitors a duty cycle of the data clock, generates a first result, and provides a timing-adjusted data clock, performs second duty cycle monitoring that monitors a duty cycle of the read clock, generates a second result, and provides a timing-adjusted read clock, calculates an offset of the read clock based on the timing-adjusted data clock, the result and the second result, and corrects a duty error of the read clock using a read clock offset code derived from the offset of the read clock.

An electronic device includes a dock dividing circuit configured to generate sampling clocks, alignment clocks and output clocks by dividing a frequency of a write clock; and a data alignment circuit configured to, in a first operation mode, receive input data having any one level among a first level to a fourth level and generate alignment data by aligning the input data in synchronization with the sampling clocks, the alignment clocks and the output clocks, and to, in a second operation mode, receive the input data having any one level of the first level and the fourth level and generate the alignment data by aligning the input data in synchronization with the sampling clocks, the alignment clocks and the output clocks.

The present disclosure relates to the field of integrated circuit technologies, and provides a method and device for testing an SR cycle as well as a method and device for testing an AR number. The method for testing an SR cycle includes: executing a preset number of data-retention-capacity acquisition steps, the data-retention-capacity acquisition step including determining a preset refresh time; sending an SR entry command to control a memory to enter an SR operation; sending an SR exit command to control the memory to exit the SR operation after the memory executes the SR for the preset refresh time; detecting a current data retention capacity of the memory; obtaining a cycle of a function of the data retention capacity with respect to the corresponding preset refresh time; and determining the SR cycle of the memory with the cycle of the function.

Technology is disclosed herein for semi receiver side write training in a non-volatile memory system. The transmitting device has delay taps that control the delay between a data strobe signal and data signals sent on the communication bus. The delay taps on the transmitting device are more precise that can typically be fabricated on the receiving device (e.g., NAND memory die). However, the receiving device performs the comparisons between test data and expected data, which alleviates the need to read back the test data. After the different delays have been tested, the receiving device informs the transmitting device of the shortest and longest delays for which data was validly received. The transmitting device then sets the delay taps based on this information. Moreover, the write training can be performed in parallel on many receiving devices, which is very efficient.

Disclosed herein is a semiconductor device including a non-volatile memory unit. The non-volatile memory unit has a subject current path disposed in a semiconductor integrated circuit and a fuse element inserted in series on the subject current path, and changes output data according to a voltage between both ends of the fuse element when supply of a subject current to the subject current path is intended. A current supply part that switches the subject current between a plurality of stages is disposed in the non-volatile memory unit.

A memory anomaly processing method and system, an electronic device, and a storage medium. The method includes: reading a memory error quantity of a target memory bank from a memory error register; when the memory error quantity is greater than a preset value, executing a hot-removal operation on the target memory bank; calculating a memory delay parameter, and writing the memory delay parameter into a memory controller, wherein the memory delay parameter is waiting time after the memory controller controls the target memory bank to receive a read/write command; and executing a hot-addition operation on the target memory bank, whereby the memory controller continues to execute a read/write operation on the target memory bank based on the memory delay parameter. It can be seen that, according to the present application, the memory read/write error rate may be reduced.

A method of operating a host device includes transmitting a read command that requests information related to an eye open monitor (EOM) operation performed in a memory device to the memory device, and receiving a response signal including the information related to the EOM operation performed in the memory device from the memory device.

Methods, systems, and devices for adjustable programming pulses for a multi-level cell are described. A memory device may modify a characteristic of a programming pulse for an intermediate logic state based on a metric of reliability of associated memory cells. The modified characteristic may increase a read window and reverse a movement of a shifted threshold voltage distribution (e.g., by moving the threshold voltage distribution farther from one or more other voltage distributions). The metric of reliability may be determined by performing test writes may be a quantity of cycles of use for the memory cells, a bit error rate, and/or a quantity of reads of the first state. The information associated with the modified second pulse may be stored in fuses or memory cells, or may be implemented by a memory device controller or circuitry of the memory device.

A method of operating a memory device includes receiving a duty training request, performing first training for a write path in a first period, storing a result value of the first training, performing second training for a write path in a second period, storing a result value of the second training, transmitting the result value of the first training to an external device, and receiving a duty cycle adjuster (DCA) code value corresponding to the first training result value from the external device.