A signal generator includes a first amplifier for outputting an amplified voltage in response to a reference voltage and a feedback voltage, a divider circuit for dividing the amplified voltage to generate a divided voltage and the feedback voltage, and a buffer group for outputting a common sensing signal in response to the amplified voltage and outputting a sensing signal in response to the divided voltage, and a memory device including the signal generator.

A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.

A memory module is operable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals and a system clock from the memory controller and to output a module clock, module C/A signals and data buffer control signals. The module C/A signals are provided to memory devices organized in one or more ranks, while the data buffer control signals, together with the module clock, are provided to a plurality of buffer circuits corresponding to respective groups of memory devices and are used to control data paths in the buffer circuits. The plurality of buffer circuits include clock regeneration circuits to regenerate clock signals with programmable delays from the module clock. The regenerated clock signals are provided to respective groups of memory devices so as to locally sync the buffer circuits with respective groups of memory devices.

A method includes requesting, by a component of a memory sub-system controller, control of a data path associated with a memory device coupleable to the controller. The method can include generating, by the component, data corresponding to an operation to test the memory device and causing, by the component, the data to be injected to the data path such that the data is written to the memory device. The method can further include reading, by the component, the data written to the memory device and determining, by the component, whether the data read by the component from the memory device matches the data written to the memory device.

A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings and configured to retain a threshold voltage. A control circuit is coupled to the word lines and strings and is configured to compute a target word line voltage including a kicking voltage to be applied to selected ones of word lines for a kick time during a read operation. The control circuit extends the kick time by a compensation time to a compensated kick time in response to determining the target word line voltage is not greater than a predetermined voltage design limit. The control circuit applies the kicking voltage to the selected ones of word lines for the compensated kick time thereby enabling a word line voltage to reach one of a plurality of reference voltages quickly without exceeding the predetermined voltage design limit.

A signal generator includes a first amplifier for outputting an amplified voltage in response to a reference voltage and a feedback voltage, a divider circuit for dividing the amplified voltage to generate a divided voltage and the feedback voltage, and a buffer group for outputting a common sensing signal in response to the amplified voltage and outputting a sensing signal in response to the divided voltage, and a memory device including the signal generator.

Methods, systems, and devices for masked training and analysis with a memory array are described. A memory device may operate in a first mode in which a maximum transition avoidance (MTA) decoder for a memory array of the memory device is disabled. During the first mode, the memory device may couple an input node of the MTA decoder with a first output node of a first decoder, such as a first pulse amplitude modulation (PAM) decoder. The memory device may operate in a second mode in which the MTA decoder for the memory array is enabled. During the second mode, the memory device may couple the input node of the MTA decoder with a second output node of a second decoder, such as a second PAM decoder.

A phase correction circuit includes a plurality of signal paths configured to transmit multi-phase signals. The phase correction circuit further includes a loop circuit coupled to the plurality of signal paths, the loop circuit configured to correct phase skew among the multi-phase signals by averaging the phases of two signals which are obtained by synthesizing a signal of each of the signal paths with another signal of a signal path different from the corresponding signal path.

The present disclosure relates to a memory device for correcting a pulse duty ratio and a memory system including the same, and relates to a memory device which corrects the duty ratio of a primary pulse of a memory device control signal, and a memory system including the same.

A system and method for measuring the degradation of one or more memory devices of a memory sub-system. An example system including a memory controller operatively coupled with a memory device and configured to perform operations comprising: testing different values for a setting of the memory device, wherein the setting of the memory device affects a duty cycle of a signal internal to the memory device; selecting an optimum value for the setting based on access errors during the testing, wherein the optimum value minimizes access errors; determining a degradation measurement for the memory device based on the optimum value; and providing a notification to a host system based on the degradation measurement.