Provided are a memory device detecting a defect and an operating method thereof. The memory device includes a memory cell area including a memory cell array that stores data, and a peripheral circuit area including a control logic configured to control operations of the memory cell array, wherein the peripheral circuit area further includes a defect detection circuit, the defect detection circuit being configured to generate a count result value by selecting a first input signal from a plurality of input signals and counting at least one time interval of the first input signal based on a clock signal, and to detect a defect of the first input signal by comparing an expected value with the count result value, and the at least one time interval is a length of time in which logic low or logic high is maintained.

A resistor-capacitor (RC) sensor circuit includes an integration capacitor configured to integrate a representative copy of a current that drives an electronic circuit line. The integration capacitor is configured to integrate over a first time period to generate a first representative voltage and over a second time period to generate a second representative voltage. The RC sensor circuit includes a sampling circuit coupled to the integration capacitor and configured to sample the first representative voltage and the second representative voltage. A ratio of the first sampled voltage and the second sampled voltage is indicative of an RC time constant of the electronic circuit line.

Embodiments of the disclosure are drawn to apparatuses and methods for soft post-package repair (SPPR). After packaging, it may be necessary to perform post-package repair operations on rows of the memory. During a scan mode of an SPPR operation, addresses provided by a fuse bank may be examined to determine if they are open addresses or if the bad row of memory is a redundant row of memory. The open addresses and the bad redundant addresses may be stored in volatile storage elements, such as in latch circuits. During a soft send mode of a SPPR operation, the address previously associated with the bad row of memory may be associated with the open address instead, and the address of the bad redundant row may be disabled.

A leakage detection circuit may include: a comparison circuit configured to compare an input voltage, which changes based on the level of an operation voltage node, to a reference voltage and configured to output a detection signal; and a state decision circuit configured to determine a count value that corresponds to a determination period based on the detection signal and configured to output leakage state information based on the count value.

Process for determining defects in cells of a circuit is provided. A layout of a circuit is received. The layout comprises a first cell and a second cell separated by a boundary circuit. Bridge pairs for the first cell and the second cell is determined. The bridge pairs comprises a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell. Bridge pair faults between the bridge pairs are modeled. A test pattern for the bridge pair faults is generated.

A non-volatile memory device includes: one or more memory blocks including a plurality of memory cells connected to a plurality of word lines, and a plurality of memory cell strings; a page buffer unit; one or more pass units including a plurality of pass transistors that may supply operation voltages to the plurality of word lines; one or more monitoring units including one or more monitoring pass transistors connected to the plurality of pass transistors; a voltage generator that may supply activation voltages to a first pass transistor, in which a leakage current is to be measured, and to the one or more monitoring pass transistors; and a control logic that may control the voltage generator to generate the activation voltages by using a voltage control signal and detect the leakage current based on monitoring voltages output from the one or more monitoring pass transistors.

Various examples of memory systems comprising an address fault detection system are disclosed. The memory system comprises a first memory array, a row decoder, and an address fault detection system comprising a second array, wherein the row decoder decodes row addresses into word lines, each word line coupled to a row of cells in the first array and a row of cells in the second array. The second array contains digital bits and/or analog values that are used to identify address faults.

A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A memory controller sends register values, for storage in a plurality of registers of a respective memory device. The register values include register values that represent one or more impedance values of on-die termination (ODT) impedances to apply to the respective inputs of the respective memory device that receive the CA signals, and one or more register values to selectively enable application of a chip select ODT impedance to the chip select input of the respective memory device.

Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.

A semiconductor memory device includes; a memory semiconductor die including a volatile memory device configured to perform a normal operation in response to at least one of a command and an address received from a host device, and a test chip vertically stacked with the memory semiconductor die and including a nonvolatile memory device. The test chip is configured in the normal mode to store log information corresponding to at least one of a command and an address received by the semiconductor memory device from the host device, and is further configured in a debugging mode to read the log information from the nonvolatile memory device.