An antifuse circuit includes a current generator and an antifuse sense unit. The current generator has at least one electronic device. The antifuse sense unit is electrically connected to the current generator, and the antifuse sense unit has at least one copied electronic device. An electronic device specification of the at least one electronic device of the antifuse sense unit is equal to an electronic device specification of the at least one copied electronic device of the current generator. The current generator supplies a current to the antifuse sense unit that senses an antifuse.

Provided are a fuse blowing method and apparatus for a memory, a storage medium, and an electronic device. The method includes: controlling a memory to enter a test mode, and reducing an internal clock frequency of the memory (S210); starting a fuse blowing load mode, and controlling the memory to enter a fuse blowing mode (S220); enabling internal precharge of the memory, and writing a location of a fuse to be blown into a fuse blowing location register (S230); starting a fuse blowing process of the memory, and disabling the internal precharge after preset time (S240); and controlling the memory to exit the fuse blowing mode and the test mode successively (S250).

Fuse logic is configured to selectively enable certain group of fuses of a fuse array to support one of column (or row) redundancy in one application or error correction code (ECC) operations in another application. For example, the fuse logic may decode the group of fuses to enable a replacement column (or row) of memory cells in one mode or application, and decodes a subset of the group of fuses to retrieve ECC data corresponding to a second group of fuses are encoded to enable a different replacement column or row of memory cells in a second mode or application. The fuse logic includes an ECC decode logic circuit that is selectively enabled to detect and correct errors in data encoded in the second group of fuses based on the ECC data encoded in the subset of fuses of the first group of fuses.

A method for determining a status of a fuse element are provided. The method includes providing the memory device including a first terminal and a second terminal; applying a first power signal on the first terminal of the semiconductor device, wherein the memory device includes a configurable reference resistor unit electrically coupled to the fuse element; obtaining an evaluation signal, in response to the first power signal, at the second terminal of the memory device; and identifying the evaluation signal to determine whether the memory device is redundant.

A one-time programmable (OTP) circuit. The OTP circuit includes a non-volatile OTP memory disposed on a first circuit die. The OTP memory includes a floating gate terminal. The OTP circuit also includes a cross-coupled latch disposed on the first circuit die and coupled to the OTP memory and volatile memory input circuitry disposed on the first circuit die and coupled to the cross-coupled latch. The volatile memory input circuitry is configured to receive a test value and write the test value into the cross-coupled latch. The OTP circuit is configured to receive a programming command and store the test value in the OTP memory in response to receipt of the programming command.

A trimming method for adjusting electrical characteristics of an adjustment circuit, which is provided in a semiconductor substrate, by cutting a fuse resistor provided in the semiconductor substrate. In a case where a cutting current flows to the fuse resistor to cut the fuse resistor, at least one of switching devices provided in the semiconductor substrate is set to a conductible state to make the cutting current flow to the switching device.

A semiconductor device includes a flag generation circuit configured to receive region fuse data and used fuse data which are generated from a fuse set selected based on a fuse set selection signal among from fuse sets and generate a bank resource flag to control a repair operation for a bank on which a repair operation has not been performed, based on the region fuse data and the used fuse data. The semiconductor device also includes a repair control circuit configured to control the repair operation for banks sharing the fuse sets based on the bank resource flag.

A semiconductor circuit and a semiconductor device for determining a status of a fuse element are provided. The semiconductor circuit includes a configurable reference resistor unit with a first terminal receiving a first power signal and a second terminal electrically coupled to the fuse element. The semiconductor circuit also includes a first switching circuit electrically connecting the configurable reference resistor unit and the fuse element and a latch circuit for reading an evaluation signal of a first node between the configurable reference resistor unit and the fuse element.

A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.

A test method of the semiconductor memory device including a memory cell array and an anti-fuse array includes detecting failed cells included in the memory cell array; determining a fail address corresponding to the detected failed cells; storing the determined fail address in a first region of the memory cell array; and reading the fail address stored in the first region to program the read fail address in the anti-fuse array. According to the test method of a semiconductor memory device and the semiconductor memory system, since the test operation can be performed without an additional memory for storing an address, the semiconductor memory device and the test circuit can be embodied by a small area.