A semiconductor device capable of performing product-sum operation with low power consumption. The semiconductor device includes first and second logic circuits, first to fourth transistors, and first and second holding units. A low power supply potential input terminal of the first logic circuit is electrically connected to the first and third transistors. A low power supply potential input terminal of the second logic circuit is electrically connected to the second and fourth transistors. The potentials of second gates of the first and fourth transistors are held in the first holding unit as potentials corresponding to first data. The potentials of second gates of the second and third transistors are held in the second holding unit. The on/off states of the first to fourth transistors are determined by second data. A difference in signal input/output time between the first and second logic circuits depends on the first data and the second data.

A command to read specific data stored at a memory die is received. A read operation is performed while operating both a memory controller and the memory die simultaneously at a first frequency. A processor determines whether a first error rate associated with the memory die satisfies a first error threshold criterion (e.g., UECC). Responsive to determining that the first error rate satisfies the first error threshold criterion, the read operation is repeated while operating at least one of the memory controller or the memory die at a second frequency that is different from the first frequency. The processor determines whether a second error rate associated with the memory die satisfies a second error threshold criterion. Responsive to determining that the second error rate satisfies the second error threshold criterion (e.g. UECC persists), determining that the read operation has failed.

A refresh time detection circuit and a semiconductor device including the same may be provided. The refresh time detection circuit may include a code generator configured to generate a code signal for detecting a refresh time. The refresh time detection circuit may include a latch circuit configured to generate a latch signal by latching the code signal according to a fail signal, and generate a pre-code signal and a post-code signal by latching each latch signal according to a pre-enable signal and a post-enable signal. The refresh time detection circuit may include a subtractor configured to output a refresh detection signal by performing subtraction between the pre-code signal and the post-code signal. The refresh time detection circuit may include a comparator configured to generate a detection signal by comparing the refresh detection signal with an offset signal based on the post-enable signal.

A method for trimming analog temperature sensors. First, raise a temperature of a temperature sensor to a highest temperature of a qualification temperature range. Then, trim the temperature sensor such that a high temperature code generated by the temperature sensor represents an actual temperature reported by the temperature sensor at the highest temperature. Next, lower the temperature of the temperature sensor to a lowest temperature of the qualification temperature range. Determine a slope error between the high temperature code and a low temperature code generated by the temperature sensor at the lowest temperature. Finally, determine a correction function that compensates for the slope error of measured temperature codes generated by the temperature sensor for temperatures across the qualification temperature range.

Methods, systems, and devices for defect detection for a memory device are described. A segmented digital die defect detector may include multiple signal lines, each coupled with a test circuit, and a control circuit to form a path. At least part of the path may extend through an internal portion of the die. A test circuit may generate a digital feedback signal that indicates a condition of a respective signal line. The control circuit may generate a single output signal, indicative of the condition of the signal lines. By utilizing digital testing circuitry and a single digital output signal, a layout area of the segmented digital die defect detector may be reduced and a power consumption associated with the testing operation may be reduced.

A method for predicting high-temperature operating life of an integrated circuit (IC) includes performing bias temperature instability tests and high-temperature operating life tests on a device of the IC, establishing a relationship between the device bias temperature instability and the IC's high-temperature operating life based on a result of the bias temperature instability tests and the high-temperature operating life tests. The method further includes providing a lot of subsequent integrated circuits (ICs), performing wafer-level bias temperature instability tests on a device of the ICs, and predicting high-temperature operating life of the ICs based on a result of the wafer-level bias temperature instability tests and based on the established relationship between the device's bias temperature instability and the IC's high-temperature operating life. The method can save significant effort and time over conventional approaches for accurate prediction of high-temperature operating life of an IC.

A memory device in which the number of films is reduced. The memory device includes a circuit and a wiring. The circuit includes a first memory cell and a second memory cell. The first memory cell includes a first transistor, a second transistor, and a first capacitor. The second memory cell includes a third transistor, a fourth transistor, and a second capacitor. The second memory cell is stacked over the first memory cell. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and the first capacitor. One of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor and the second capacitor. A gate of the first transistor and a gate of the third transistor are electrically connected to the wiring.

Systems and methods for correcting data errors in memory caused by high-temperature processing of the memory are provided. An integrated circuit (IC) die including a memory is formed. Addresses of memory locations that are susceptible to data loss when subjected to elevated temperatures are determined. Bits of data are written to the memory, where the bits of data include a set of bits written to the memory locations. The set of bits are written to a storage device of the IC die that is not susceptible to data loss when subjected to the elevated temperatures, the subset of bits comprise compressed code. At least one of the bits stored at the addresses is overwritten after subjecting the IC die to an elevated temperature. The at least one of the bits is overwritten based on the set of bits written to the storage device.

Many error correction schemes fail to correct for double-bit errors and a module must be replaced when these double-bit errors occur repeatedly at the same address. This helps prevent data corruption. In an embodiment, the addresses for one of the memory devices exhibiting a single-bit error (but not the other also exhibiting a single bit error) is transformed before the internal memory arrays are accessed. This has the effect of moving one of the error prone memory cells to a different external (to the module) address such that there is only one error prone bit that is accessed by the previously double-bit error prone address. Thus, a double-bit error at the original address is remapped into two correctable single-bit errors that are at different addresses.

According to a first aspect of the present invention, there is provided a method, a computer system and a computer program product. The method, computer system and computer program product including measuring an initial state of a set of SRAM bits on the wafer, identifying a first set of signature SRAM bits on the wafer, of the set of SRAM bits on the wafer, where the first set of SRAM bits comprise a consistent initial state greater than a first threshold percentage of times, measuring physically dimensions of features of the first set of SRAM bits on the wafer; and identifying a set of signature SRAM bits of the first set of SRAM bits on the wafer, wherein the set of signature SRAM bits comprise physical dimensions of features which correlate to the initial state of each correlated SRAM bit.