An apparatus includes a static random-access memory and circuitry configured to initiate a corrective action associated with the static random-access memory. The corrective action may be initiated based on a number of static random-access memory cells that have a particular state responsive to a power-up of the static random-access memory.

Methods and apparatus for dynamically adjusting performance of partitioned memory. In one embodiment, the method includes receiving one or more configuration requests for the memory device, determining whether to grant the one or more configuration requests for the memory device, in response to the determining, implementing the one or more configuration requests within the memory device and operating the memory device in accordance with the implementing. The adjusting of the performance for the partitioned memory includes one or more of enabling/disabling refresh operations, altering a refresh rate for the partitioned memory, enabling/disabling error correcting code (ECC) circuitry for the partitioned memory, and/or altering a memory cell architecture for the partitioned memory. Systems and applications that may benefit from the dynamic adjustment of performance are also disclosed.

Various examples of the present technology provide systems and methods for tracking PPR usage in dual in-line memory modules (DIMMs) of a server system. BIOS of the server system can check a record of the PPR usage before conduct a PPR flow and send a usage status of spare row(s) of a plurality of bank groups of a DIMM to a controller (e.g., BMC) of the server system such that a user or the server system can check PPR status of each DIMM of the server system. A determination can be made either automatically by the server system or manually by the user whether or not to replace a corresponding

Disclosed is a system including a memory device having a plurality of physical cells and a processing device, operatively coupled with the memory device, to perform operations that include selecting, responsive to detecting a power event, a subset of a plurality of memory cells of the memory device, the memory device being characterized by auxiliary read metadata identifying one or more read offsets for each of the plurality of memory cells, the one or more read offsets representing corrections to read signals applied to the respective memory cell during a read operation. The operations further include performing one or more diagnostic read operations for each of the subset of the plurality of memory cells of the memory device and modifying the auxiliary read metadata by updating the one or more read offsets for at least some of the plurality of memory cells of the memory device.

An electrical device (e.g., an integrated circuit) includes an amplifier, a configurable common mode gain trim circuit, and a memory. The configurable common mode gain trim circuit is coupled to the amplifier. The memory is configured to include trim data that is usable during an initialization process for the electrical device to configure the impedance matching circuit.

A memory device includes a system block for storing test information and includes a data block including memory cells connected to a plurality of low bank column lines and a plurality of high bank column lines. The memory device also includes a column repair controller configured to detect, based on the test information, a concurrent repair column line in which a low bank column line among the plurality of low bank column lines and a high bank column line the plurality of high bank column lines corresponding to the same column address are concurrent repaired.

A method of repairing a storage device including a non-volatile memory includes powering on the storage device, performing a booting sequence, determining whether an error has occurred during the booting sequence or during a normal mode, writing a failure signature to a predetermined signature address in the non-volatile memory upon determining that the error has occurred, reporting a failure to a host upon writing the failure signature, entering into a repair mode upon reporting the failure, and operating in the normal mode upon determining that the error has not occurred.

An arrangement to guarantee boot up of a computer includes a control center microchip with BIOS boot block and BIOS program, and a flash memory divided into a first protected block, a main block, and a second protected block. In the computer, an embedded controller (EC) with stored modules is electrically connected to the flash memory and the control center microchip. The modules include a determining module to check that the code of the first protected block is identical with the code of the second protected block and a recovery module able to reinstate correct code from the second protected block into the first protected block if required. A method applied to the disclosed computer startup detection system is also disclosed.

In an embodiment, a processor includes at least one core to execute instructions and a memory controller coupled to the at least one core. In turn, the memory controller includes a spare logic to cause a dynamic transfer of data stored on a first memory device coupled to the processor to a second memory device coupled to the processor, responsive to a temperature of the first memory device exceeding a thermal threshold. Other embodiments are described and claimed.

Detecting a defective cell in a memory in consideration of an error property difference depending on the storage state. A determination unit determines whether there is a possibility of defect for each of unit-of-storages on a memory cell formed with a non-volatile memory. The non-volatile memory undergoes either a reset operation that transitions a state from a low resistive state (LRS) to a high resistive state (HRS) or a set operation that transitions the state from the high resistive state to the low resistive state. The determination unit determines a unit-of-storage in which the number of errors in predetermined one of the reset operation and the set operation has exceeded a predetermined standard, as a unit-of-storage suspected of having a defect.