According to one embodiment, an electromagnet includes a first electromagnet coil having a first portion and a second portion. The first portion of the first electromagnet coil extends in a direction in parallel with a first plane. The second portion of the first electromagnet coil extends in a direction in parallel with a second plane. The first and second planes intersect at a predetermined angle.

A ground bounce generator includes a resistor and at least one switch coupled in parallel with the resistor. The ground bounce generator is in a device under test circuit including a source, at least one ground bounce generator, at least one device under test, and a ground. The device under test is coupled in series between the source and the ground bounce generator. The device under test and the ground bounce generator are coupled in series between the source and the ground.

A signal input/output circuit is provided with an input line, a common output line, a plurality of individual output lines, relay switches, and resistor elements. The common output line is connected to a comparator. The common output line synthesizes response signals transmitted from a plurality of devices under test (DUT), and transmits a synthesized response signal generated by synthesizing, into one signal, the response signals outputted from the respective DUTs. In response to a test signal transmitted from a pattern generator, the comparator compares the synthesized response signal with a threshold value.

The present invention relates to a system level test device for memory. A memory module system level tester device according to the present invention makes the motherboard and the memory modules be in contact with each other by using the test tray, thereby minimizing a time required for attaching and detaching the memory modules and omitting an additional configuration for attaching and detaching the memory modules. Accordingly, space limitations can be minimized, and as a result, test units can be arranged in two or more stages in the vertical direction to configure a compact layout to thereby increase space efficiency.

The embodiments of the present application provide a test board, which is applied in temperature and humidity tests for a memory module, and includes: a memory slot configured to be connected with the memory module; a power supply terminal configured to supply power to the memory module; an overcurrent protection unit connected in series between the memory slot and the power supply terminal and configured to be blown when the memory module is short-circuited; and an indicating unit connected in series between the overcurrent protection unit and a ground terminal and configured to indicate a state of the overcurrent protection unit. The embodiments of the present application provide a test board capable of indicating temperature and humidity test results.

A protection circuit can be applied in a chip, and include: a first protection unit and a first element to be protected, wherein the first protection unit is configured to receive a first input signal and a control signal, and is configured to output a first output signal, the first element to be protected includes a first P-type transistor, and a gate of the P-type transistor is configured to receive the first output signal. When the chip enters a burn-in test, the first output signal is a high-level signal.

A test system is disclosed. The test system includes a tester, a first voltage stabilization circuit, and a device under test (DUT). The tester generates a first operational voltage and a control signal. The first voltage stabilization circuit transmits a second operational voltage, associated with the first operational voltage, to a socket board. The DUT operates with the second operational voltage received through the socket board. The first voltage stabilization circuit is further configured to control, according to the control signal, the second operational voltage to have a first voltage level when the DUT is operating.

A thermal chamber includes a cavity that is enclosed by sides and one or more ports that expose the cavity within the thermal chamber. Each of the one or more ports is configured to receive a temperature control component having a solid physical structure and configured to transfer thermal energy to and from an electrical device exposed via the cavity. The thermal chamber includes a bottom side open area of the thermal chamber located below the one or more ports. The bottom side open area is configured to allow the temperature control component to contact the electrical device that is exposed via the bottom side open area.

A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.

A device is disclosed for testing a memory, in which the memory includes a first memory circuit and a second memory circuit. The second memory circuit is configured to store a first response in responses of the first memory circuit, and the first memory circuit is configured to store a second response of responses of the second memory circuit. The device includes a comparing circuit and a maximum hamming distance generating circuit. The comparing circuit is configured to compare the first response with the responses of the first memory circuit, and configured to compare the second response with the responses of the second memory circuit, to generate comparing results. The maximum hamming distance generating circuit is configured to generate a maximum hamming distance according to the comparing results.